Vendor: Small World Communications Category: Channel Coding

TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder

This is a fully compatible TETRA-TEDS error control decoder.

Overview

This is a fully compatible TETRA-TEDS error control decoder. The decoder can be used to decode the standard 8 state turbo code and 16 state convolutional code. The PCD03T offers paralleleled speed, performance, low complexity and features compared to other available decoder cores.

Key features

  • Turbo Decoder
    • 8 state TETRA-TEDS compatible
    • Rate 1/2 or 1/3
    • 2 to 6144 bit interleaver
    • Up to 145 MHz internal clock
    • Up to 13.8 Mbit/s with 5 decoder iterations
    • 6-bit signed magnitude input data
    • Optional log-MAP or max-log-MAP constituent decoder algorithms
    • Up to 32 iterations in 1/2 iteration steps
    • Optional power efficient early stopping
    • Optional extrinsic information scaling and limiting
    • Estimated channel error output
  • Viterbi Decoder (Optional)
    • 16 state (constraint length 5)
    • Rate 1/4
    • Data lengths from 2 to 8188 bits with tail termination of 4 zero data bits
    • Up to 11.5 Mbit/s
    • 6-bit signed magnitude input data
    • Estimated channel error output
  • Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6 and Spartan-6 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
  • Available as VHDL core for ASICs
  • Low cost university license also available

What’s Included?

  • All licenses
  • EDIF core
  • VHDL simulation core
  • Test vector generation software
  • VHDL ASIC License
  • VHDL ASIC core
  • C++ bit/cycle exact simulation model

Specifications

Identity

Part Number
PCD03T
Vendor
Small World Communications
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about Channel Coding IP cores

What is TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder?

TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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