Vendor: EnSilica Category: Channel Coding

High Throughput Reed Solomon Decoder

This is a Reed Solomon decoder capable of operating with shortened codewords.

Overview

This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes and can correct up to 8 corrupted bytes (up to 8 bits in a byte can be in error). The mother rate can be shortened to N_MAX <= 255 but still retains the ability to correct up to 8 bytes in error. The decoder only outputs K bytes per N bytes in, and these are in natural order. It has enough memory to operate continuously with one byte per clock cycle on its input, leading to a net rate of 8*CLK bps of coded data. The codeword length is programmable at run-time.

Key features

  • Based on industry standard generating polynomials
  • Supports shortening
  • Supports erasures
  • Run-time programmable codeword length
  • High throughput

Benefits

  • Low memory usage
  • Low gate-count

What’s Included?

  • RTL
  • Testbench
  • Synthesis scripts
  • Documentation
  • MATLAB and C++ bit exact model

Specifications

Identity

Part Number
eSi-ReedSolomon-HT
Vendor
EnSilica
Type
Silicon IP

Provider

HQ: UK

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Frequently asked questions about Channel Coding IP cores

What is High Throughput Reed Solomon Decoder?

High Throughput Reed Solomon Decoder is a Channel Coding IP core from EnSilica listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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