Memory interface IP cores provide the critical connectivity layer between processing elements and memory devices, enabling high-bandwidth, low-latency, and power-efficient data access in modern SoC, ASIC, AI, networking, and high-performance computing designs.
This category includes DDR, LPDDR, GDDR, HBM, NAND Flash, and NOR Flash interface IP solutions, covering memory controllers, PHYs, controller-PHY subsystems, training engines, calibration logic, and complete memory interface architectures. These IP cores are designed to maximize memory bandwidth, optimize latency, ensure signal integrity, and simplify integration across advanced semiconductor process nodes.
LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
SDRAM Controller DO-254 IP Core
The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as…
The Reduced Latency Dynamic Random Access Memory (RLDRAM) Controller is a general-purpose memory controller that interfaces with …
A Lattice FPGA based LPDDR3 solution – The Lattice Low Power Double Data Rate (LPDDR3) Synchronous Dynamic Random Access Memory (…
The LPDDR Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with…
Fast Cycle RAM (FCRAM) is a DRAM technology with a specialized memory core technology that achieves faster random access times an…
The Lattice Double Data Rate (DDR3) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory contr…
The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3…
DDR/DDR2 SDRAM Controller MACO Core
The DDR/DDR2 Synchronous Dynamic Random Access Memory (SDRAM) Controller MACO Core is a general-purpose memory controller that in…
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.
DDR SDRAM Controller - Non-Pipelined
This version of the Lattice DDR SDRAM Controller does not have pipelining, and is significantly smaller than the pipelined versio…
DDR-I/II/III CONTROLLER IP CORE
DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targ…
The SRAM-CTRL implements a Static Random Access Memory (SRAM) Controller translating AHB, or AXI4, or APB bus reads and writes in…
DDR2 SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
DDR SDRAM Controller - Pipelined
The Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller tha…
DDR SDRAM Controller
LPDDR6 PHY & Controller