relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
By Michael Rogenmoser, Angelo Garofalo and Luca Benini (ETH Zurich)
Abstract
On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care in radiation-heavy environments, as any soft error within the SoC interconnect is likely to cause a functional failure of the whole SoC. This work proposes relOBI, an extension to Open Bus Interface (OBI) combining triple modular redundancy (TMR) for critical handshake signals with error correction codes (ECC) protection on other signals for complete reliability. Implementing and testing a fully reliable crossbar shows improved reliability to injected faults from a vulnerability of 34.85 % to 0 % compared to a reference design, with an area increase of 2.6x and 1.4x timing impact. The area overhead is 1.8x lower than that reported in the literature for fine-grained triplication and voting.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- NoC Verification IP
- FlexGen Smart Network-on-Chip (NoC) IP
- NoC System IP
- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
Related Articles
- A 'network-centric' approach to on-chip interconnect
- On-Chip Interconnect Costs Spawn Research
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- CompactPCI Interconnect Spec To Be Enhanced
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing