NoC System IP

Reduce Risk and Improve Productivity

In a business environment, where design timelines are shrinking, while the need for custom solutions increases, design teams are relying more than ever on reputable, reliable IP solutions. With this increasing complexity, connectivity fabric complexity also increases. Cadence Janus NoC System IP, a highly configurable, high-performance, network-on-chip IP, addresses this complexity, from the subsystem level all the way up to multi-chiplet systems.

IP solutions are needed to address complexity and allow design teams to focus on the critical elements that differentiate their design. The Cadence Janus NoC can be configured with little effort using state-of-the-art GUI tools while power, performance, and area (PPA) metrics can be verified and further optimized by using Cadence simulation/emulation solutions.

Simple and Efficient Interconnect for the Most Complex SoC Designs

• Reduces wire count and congestion
• Reduces physical design issues
• Handles gear change automatically
• Configurable to meet your PPA goals
• Easy to configure with a quick turnaround of configuration changes
• Use with Cadence simulation/emulation to identify bottlenecks and remove them

Intuitive Design Entry Tool

• Use a powerful GUI to generate a NoC configuration, then submit the configuration to get RTL and SystemC models

Highly Configurable

• Configure BW, latency, clock domain crossings, clock gating, buffer size, and pipeline stages—everything you need to achieve your target PPA goals

Scalability

• Start with subsystem design, then take the same design and create a full SoC; Need a higher level of integration? No problem, we can do chiplets as well