On-Chip Interconnect Costs Spawn Research
Deepak Sekar, Zsolt Tőkei, and Vincent McGahay (Rambus)
EETimes (3/26/2014 07:05 PM EDT)
With 16nm chips moving to production this year, companies are actively developing the 10nm and 7nm technology nodes. These generations are interconnect heavy -- more than 50% of their cost is due to the back-end-of-line (BEOL) wiring levels, and designs are dominated by interconnect delay. Engineers are taking several paths to get around this trend, many of which will be discussed at the IITC Advanced Metallization Conference in May in San Jose.
First, interconnect performance and reliability depends heavily on diffusion barriers, liners, and cap layers for copper. These can be improved in multiple ways.
For example, engineers can make these structures thinner and improve their quality by using CVD or ALD instead of PVD and by using alternative materials. At the May conference, researchers from IBM and Applied Materials will present results of their work on multi-layer SiN caps and cobalt caps and liners that provide a 1000x improvement in electromigration lifetime, as well as enhancements in time-dependent dielectric breakdown.
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