Correct by Construction and Other Myths
Joseph Davis, Mentor Graphics
EETimes (10/28/2015 03:18 AM EDT)
"Usability" shows up on a benchmark list, "Integration" doesn't. Maybe it should.
At a certain level, we can view modern chip design methodology as based on the successive-approximation method—abstract the pieces with models, put the models together to get approximately what you want, push the design down to the next level of abstraction to see if it still works with a little more detail, then repeat until you have sufficient confidence that you can take the result to silicon. There are many, many layers of these models and abstractions, from simple transistor behavior all the way up to functional models of entire blocks. Many of these models and abstractions, and the software that embodies them, come from years of hard work by many people around the world. The objective of all that work was to find the perfect model that is accurate enough and fast enough to provide satisfactory results in a reasonable amount of time. This is all good engineering, and even some good science, too.
To read the full article, click here
Related Semiconductor IP
- nQrux® Root of Trust IP
- AXI to UCIe Bridge IP
- UCIe 2.x Controller IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
Related Articles
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
Latest Articles
- Automated Pre-Silicon Verification of High-Speed DDR5 and LPDDR5/6 Memory Controllers: Closed-Loop Timing, Mode Register, and PHY Synchronization in UVM
- U-Sonic: An Open-Source 8-Channel Ultrasound Transmit IP in a 130 nm RISC-V SoC
- S-ALSA: Co-Design of Adiabatic Logic-based Sensing and Balanced Bit-Cells for Secure and Energy-Efficient MRAM
- MEGATRON: a 28nm Analog PCM CiM/Digital System-on-Chip for Edge GenAI at 57.5 TOPS/W and 1.52 Mparam/mm²
- Peregrino: A Full-Hardware Accelerator for the Complete Falcon Post-Quantum Digital Signature Scheme on Resource-Constrained Edge Devices