D2D IP Listing

Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.

• UCIe

The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.

• UCIe

The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.

• UCIe

High-performance, low-latency PHY for D2D connectivity The UltraLink™ Die-to-Die (D2D) PHY enables SoC providers to deliver more …

• GlobalFoundries
• 12nm
• LP
• Silicon Proven

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• TSMC
• 28nm

Custom die-to-die interface in 12/16nm process technology.

• Custom
• Silicon-Proven
• Immediate
• Numerous I/O Standards

The UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe- (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 spec…

• UCIe

The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…

• Custom

A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.

• TSMC
• 16nm

The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.

• TSMC
• 16nm
• FFC

The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.

• Samsung
• 8nm

The Racyics UCIe PHY is an energy-efficient chiplet interconnect IP solution for consumer and automotive applications.

• GlobalFoundries
• 22nm
• FDX

Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge

• CPU

The NeuraScale Scalable Switch Fabric is a WeaveIP™ system IP solution that is designed from the ground-up to provide non-blockin…

• Bus Fabric

The second-generation high-performance RISC-V CPU delivers a major leap in compute capability, designed for deployment across dat…

• CPU

Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…

• UCIe

Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…

• UCIe

BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.

• Custom

IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.

• TSMC
• 5nm
• N5FF

The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…

• UCIe