IBM 65nm Low Leakage Process 24 Bit Stereo Sigma-Delta ADC/DAC
The I65LPEV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifi…
SMIC 65nm Low Leakage Process 24Bit Stereo Sigma-Delta ADC/DAC
The S65LLV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifie…
Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding.
Triple HD-video AFE digitizer - 10bits/170Mhz - 8bits/205Mhz
This macro is a triple-channel, 8/10-bits video analog front end (AFE) that incorporates all of the functions required to digitiz…
Video LVDS SerDes Transmitter-Receiver IP Core
The Video LVDS SerDes Transmitter / Receiver IP Core provides a , easy-to-use Serializer/Deserializer (SerDes) solution to interf…
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.
Avalon Multi-port SDRAM Memory Controller IP Core
The Microtronix Avalon Multi-port SDRAM Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II…
USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
USB 2.0 HOST/DEVICE/OTG Transceiver is a fully integrated PHY Core which is a super-set of HOST and DEVICE PHY with High Speed (H…
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) an…
USB 2.0 DEVICE Transceiver is a fully integrated PHY Core which is a super-set of DEVICE PHY with High Speed (HS), Full-Speed (FS…
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
High-Performance AXI to UCIe FDI Interface IP for Scalable System Integration
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
DisplayPort (DP) 1.4a / Embedded DisplayPort (eDP) 1.4a TX PHY
The DP/eDP Combo TX PHY IP is compliant to the DisplayPort v1.4a and embedded DisplayPort v1.4a.
Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®
UCIe PHY IP with X16 data width for standard package and up to 8 Gbit/s per pin data rate
The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.
The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.
Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
As real-time workloads—from high-frequency trading to low-latency AI and edge analytics—push system responsiveness to the limit, …
Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
As real-time workloads—from high-frequency trading to low-latency AI and edge analytics—push system responsiveness to the limit, …