DisplayPort and HDMI Transmit technologies are complex mixed signal designs which require both high performance analog design (eq…
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Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
DisplayPort and HDMI Transmit technologies are complex mixed signal designs which require both high performance analog design (eq…
The DisplayPort Transmistter IP core is fully compliant with DisplayPort 1.1a with HDCP content protection specifications.
The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY.
Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
TinyCore is a DSP core that supports stream-based processing of time domain audio or control data samples including single cycle …
Direct Memory Access (DMA) is a technique for transferring blocks of data between system memory and peripherals without a process…
Gamma correction is a type of pre-distortion correction made to images or video frames to offset the non-linear behavior of displ…
Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY)
Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video…
The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revi…
Numerically Controlled Oscillator
Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), offer several advantages over other type…
The function of this core is to correlate an incoming data stream to a stored binary pattern called a code sequence or coefficien…
CORDIC (COordinate Rotation DIgital Computer) is a simple and efficient algorithm to calculate hyperbolic and trigonometric funct…
Cascaded Integrator-Comb (CIC) Filter
Cascaded Integrator-Comb (CIC) filters, also known as Hogenauer filters, are used to achieve arbitrary and large sample rate chan…
Multi-Rate Serial Digital Interface (SDI) PHY Layer
As the proliferation of HDTV, IPTV and VoD streaming continues, together with the increased functionality and decreasing costs of…
JEDEC Standard No.
PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platf…
Digital Video Broadcasting - (DVB-ASI) IP Core
Digital Video Broadcasting (DVB) is a suite of open standards for digital television.
The SFI-5 Intellectual Property (IP) core enables user instantiation of an OIF-compliant SERDES Framer Interface Level 5 (SFI-5) …
Common Public Radio Interface - IP Core
This document provides technical information about the Lattice Common Public Radio Interface (CPRI) IP core.
XAUI 10Gb Ethernet Attachment Unit Interface
10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to…
The 2.5Gb MAC core can support data rates of 1Gbps or 2.5Gbps in LatticeSC/M™ devices.