Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of…
- PLL
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of…
1Kbyte EEPROM IP with configuration 64p8w16bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1 Kbyte (16(bit per word) x 8…
36Kbyte EEPROM IP with configuration 288p32w32bit
The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 36Kbyte (32(bit per word) x 3…
3.6Kbit EEPROM IP with configuration 28p8w16bit
GF130_EEPROM_01 is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6Kbit, which is organ…
1-VIA’s VSCOM4L400A6BITNMOSCALDAC IP is a 100MSa/s 6-bit Calibration DAC providing an output voltage with high linearity across a…
SMBUS & PMBUS Master/Slave controller
The DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities.
Dual-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
WAVE677DV is a 4K/8K multi-standard video codec HW IP that supports AV1, HEVC/H.265, AVC/H.264, and VP9 video codec standards.
1-VIA’s VSCOM4L400A8BITCALDAC IP is an 200MSa/s 8-bit Calibration DAC providing an output voltage with high linearity across a wi…
Spatial image transformation accelerator
The Spatial image transformation core is a signal processing accelerator designed for single or multi-channel image manipulations…
12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Intercon…
PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
This PCIe 3.0 PHY complies with the PCIe 3.0 Base Specification and supports the PIPE 4.3 interface specification.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 55LL
The combined PHY complies with the Peripheral Component Interconnect Express (PCIe), Serial ATA, USB, USB 3.0, and USB 2.0 interf…
6 Mhz to 5.8Ghz RF Power Amplifer
The CC-204IP Wideband Power Amplifier is a paralleled, multi-stage RF Power Amplifier that possesses a variable 6Mhz to 5.8Ghz ou…
6Mhz to 5.8Ghz wideband half and full wave rectifier
The CC-205IP Wideband CMOS RF Rectifier is a CMOS full wave rectifier with a 6Mhz to 5.8Ghz rectification frequency range capabil…
JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 28HPC
The JESD204B.01 version specification is compatible with the JESD204B Tx-Rx PHY IP interface, which offers support for the JESD20…
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 14SF++
In addition providing support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is consistent wi…
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP
Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via…
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 28HPC+
The JESD204B Tx-Rx PHY IP Core, compliant with the JESD204B.01 version specification offers support for the JESD204B synchronous …
12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specificat…
Provides up-to 50% area reduction and reduced power consumption by a factor ten ive compared to high-density SRAM