Movellus Brings Power Optimization IP to Samsung Electronics’ Advanced Nodes
Equips AI and HPC chip designers with on-die power optimization and advanced telemetry IP to unlock next-generation power efficiency.
Vendor:
Movellus, Inc.
Category:
PLL
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of…
Overview
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of the Movellus Aeonic™ platform. Designed for high reliability and fully SCAN enabled, the CGM provides extensive visibility and controllability of key clocking metrics.
The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.
The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.
Key features
- Process portable
- Proven (65nm to 3nm)
- Full SCAN testable
- Core voltage supply
- Low power
- Detailed debug hooks
- Multi-instance
- Ultra-low voltage
- Fine grain frequency control as low as 1 kHz steps
Benefits
- Customer Configurable
- Trade-off power vs. jitter for your application's needs
- Wide Voltage & Frequency Range
- Operating from near-threshold up to 1.6V
- Up to 8X Smaller Area
- Synthesizable implementation shrinks area proportionally with descending process nodes
Applications
- AI processors
- CPU
- GPU
- Vision processing
- Crypto mining
- Memory pooling
- Satellite
- Edge AI
- Aerospace
- Automotive
What’s Included?
- Soft IP
Specifications
Identity
Part Number
Aeonic Generate Clock Generation Module (CGM)
Vendor
Movellus, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about PLL IP cores
What is Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions?
Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions is a PLL IP core from Movellus, Inc. listed on Semi IP Hub.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.