Vendor: Movellus, Inc. Category: PLL

Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions

The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of…

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Overview

The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality clock synthesis IP that is part of the Movellus Aeonic™ platform. Designed for high reliability and fully SCAN enabled, the CGM provides extensive visibility and controllability of key clocking metrics.

The CGM is constructed using Movellus’ patented TrueDigital™ technology. The product is delivered as soft IP and implemented using the customer’s standard cell library. With proven process portability (65 nm to 3 nm) and minimal area footprint, the CGM is ideally suited for large scale distribution within an SoC.

Key features

  • Process portable
  • Proven (65nm to 3nm)
  • Full SCAN testable
  • Core voltage supply
  • Low power
  • Detailed debug hooks
  • Multi-instance
  • Ultra-low voltage
  • Fine grain frequency control as low as 1 kHz steps

Benefits

  • Customer Configurable
  • Trade-off power vs. jitter for your application's needs
  • Wide Voltage & Frequency Range
  • Operating from near-threshold up to 1.6V
  • Up to 8X Smaller Area
  • Synthesizable implementation shrinks area proportionally with descending process nodes

Applications

  • AI processors
  • CPU
  • GPU
  • Vision processing
  • Crypto mining
  • Memory pooling
  • Satellite
  • Edge AI
  • Aerospace
  • Automotive

What’s Included?

  • Soft IP

Specifications

Identity

Part Number
Aeonic Generate Clock Generation Module (CGM)
Vendor
Movellus, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Movellus, Inc.
HQ: USA
Contact Movellus, Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions?

Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions is a PLL IP core from Movellus, Inc. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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