What is Spatial image transformation accelerator?
Spatial image transformation accelerator is a Image Conversion IP core from Institute of Electronics and Computer Science listed on Semi IP Hub.
Vendor:
Institute of Electronics and Computer Science
Category:
Image Conversion
Spatial image transformation accelerator
The Spatial image transformation core is a signal processing accelerator designed for single or multi-channel image manipulations…
Overview
The Spatial image transformation core is a signal processing accelerator designed for single or multi-channel image manipulations based on matrix multiplication. The core is packaged as an AXI-Stream compatible accelerator, which features a bi-cubic interpolation for reconstruction and parallel access to embedded dual port memory resources for row buffering. RGB or single channel pixel patterns with 8/10/12 bit depths are available for configuration and resolution is adjustable post implementation. Resource critical parameters, such as memory size, are variable to optimize the architecture for different types of transformations.
The Spatial image transformation core is packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the module allowing the designer to adjust for different image processing pipelines.
The Spatial image transformation core is packaged for the Xilinx IP Integrator tool and can be combined with other Xilinx IP cores. The parameters are completely configurable in the module allowing the designer to adjust for different image processing pipelines.
Key features
- Streaming is compatible with AXI-Stream protocol
- Transformation and image dimension parameters are configurable through AXI4-Lite
- Configurable image resolution and transformation coefficients supporting resolutions - up to 8192x8192.
- Single channel or RGB pixel patterns
- Supports 8/10/12 bit depths
- Available for Xilinx Vivado® IP Integrator
Block Diagram
EDI-TR block diagram
Benefits
- Can be integrated with other AXI-Stream compliant image processing cores
- Input and output dimensions are configurable independently for convenient resizing operations
- Efficient buffering with parallel memory access scheme
Applications
- Image geometric transformations, resizing and cropping
What’s Included?
- Encrypted IP Integrator core
- Testbench
- Test case
- Documentation
Specifications
Identity
Part Number
EDI-TR
Vendor
Institute of Electronics and Computer Science
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Frequently asked questions about image conversion IP cores
How should engineers evaluate this Image Conversion?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Image Conversion IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.