High-Speed LVDS (SERDES) Transceiver
The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applicatio…
- Single-Protocol PHY
High-Speed LVDS (SERDES) Transceiver
The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applicatio…
4 channel SERDES operating at up to 6.25Gbps for XAUI, RXAUI and SGMII (40nm TSMC)
PSI6254XRX is a 4 channel SERDES capable of providing XAUI (10G Attachment Unit Interface), RXAUI (10G Reduced Attachment Unit In…
Multi Protocol SERDES operating at up to 12.5Gbps (40nm TSMC)
PSI1250MP is a multi-protocol SERDES capable of operating at up to 12.5Gbps.
The 112G SerDes IP is a high-performance, multi-standard serializer/deserializer solution optimized for various reach profiles and advanced packaging architectures.
1.25 Gbps-16 Gbps HSS for Supporting Multiple Protocols
The 12.5 Gbps to 16 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
1.25 Gbps-12.5 Gbps HSS for Supporting Multiple Protocols
The 1.25 Gbps to 12.5 Gbps high-speed SerDes (HSS) is compatible with multiple industry protocols.
32 Gbps PCIe-class links, 4-tap Tx FIR, CTLE, 12-tap DFE, 30 dB IL target
Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development
A 32Gbps SerDes PHY in GlobalFoundries 22FDX withlow-jitter, half-rate tran mission, and a configurable CTLE-based receiver.
20G MSS (Multi-standard SerDes) PHY
20G MSS (Multi-standard SerDes) PHY
Empowering customers to thrive in the AI Era, INNOSILICON™ introduces its most 112G SerDes (Serializer/Deserializer) and Controll…
As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (PPA-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
A Wirebond and FlipChip compatible
With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…
4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps