AMBA Bus Host to eSPI Controller/Target
eSPI Controller/Target RTL SystemVerilog IP Core
- SPI / QSPI XSPI
Digital Blocks is a leading developer of silicon-proven semiconductor Intellectual Property (IP) cores for developers requiring best-in-class IP for AMBA Peripheral such as Multi-Channel DMA / I3C / I2C / xSPI / eSPI Controllers, LCD / OLED Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines, LVDS Display Link Layer Drivers, Video Signal & Image Processing, and Low-Latency UDP & RTP Hardware Protocol Stacks.
We offer synthesizable RTL Verilog & SystemVerilog IP Cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers. At Digital Blocks we are both System Architects and ASIC/FPGA designers. Thus, we provide IP Cores with deep system-level capabilities.
Building on our IP cores, Digital Blocks design services can customize the IP core to your unique requirements.
AMBA Bus Host to eSPI Controller/Target
eSPI Controller/Target RTL SystemVerilog IP Core
AMBA Bus Host to eSPI Controller
The Digital Blocks DB-eSPI-Controller-AMBA is a fully compliant Intel Enhanced Serial Peripheral Interface (eSPI) Base Specificat…
eSPI Target RTL SystemVerilog IP Core
The DB1881AHB IP Core interfaces a Camera CMOS Image Sensor to Frame Buffer Memory via the AMBA AHB Interconnect.
The DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL…
The DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC …
Color Space converter & Chroma Resampler- 4:4:4 RGB to 4:2:2 Y’CbCr
The DB1825 Color Space Converter & Chroma Resampler Verilog IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr…
4:4:4 Y’CbCr to 4:2:2 Y’CbCr Chroma Resampler (ITU-R BT.601)
The DB1820 Chroma Resampler IP Core down converts 4:4:4 Y’CbCr to 4:2:2 Y’CbCr in accordance with the ITU-R BT.601 standard requi…
The DB1810 Color Space Converter IP Core transforms three color components from one color space to another.
SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave …
SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfer…
I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus.
The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AX…
I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) …
I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration…
I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP desig…
BitBLT Graphics Hardware Accelerator (Avalon Bus)
The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from comma…
2D Graphics Hardware Accelerator (AHB Bus)
The Digital Blocks DB9200AHB 2D Graphics Hardware Accelerator Verilog IP Core renders graphics frames as follows: Generates bitma…
2D Graphics Hardware Accelerator (AXI Bus)
The Digital Blocks DB9200AXI 2D Graphics Hardware Accelerator / Engine Verilog IP Core renders graphics frames as follows: Genera…