High-Throughput Multi-Channel DMA Controller

The Digital Blocks DB-DMAC-MCn-AXI5-HT SystemVerilog RTL IP Core is a high-throughput Scatter Gather (SG) Direct Memory Access (DMA) Controller with AMBA AXI5 Manager interfaces, a build-time number of independent DMA Channels (1 to 126) and a DMA data path of 64 to 1024 bits. It adds the AXI5 throughput features - unique IDs with out-of-order completion, read data chunking, the Busy indicator, QoS Accept and Max_Transaction_Bytes - to the DB-DMAC-MCn-AXI4-HT engine, so the interconnect and memory can keep up with a controller that already runs close to the full bus rate.

The inherited engine is measured: at 128 bits two channels use 97.6 % of the AXI4 bus, one channel holds 73 % at a 200-cycle read latency, and descriptor nodes are 2 cycles apart. The AXI5-HT keeps those mechanisms and lifts the limits that remain: one data ID per channel becomes a pool of unique IDs, so a channel's reads and writes complete out of order; wide reads come back in 128-bit chunks in any order; and the outstanding limit and channel arbitration follow the interconnect's Busy and QoS Accept signals. Every AXI5 feature is a build or register option; with all of them off the core behaves as the DB-DMAC-MCn-AXI4-HT.

High-Throughput Engine (from DB-DMAC-MCn-AXI4-HT, measured) 

• Decoupled write path: AW runs ahead of W through a queue; W bursts go back-to-back 
• Read-space reservation: buffer space is claimed when a read is issued, so RREADY is constant 1 - no  read stalls, no head-of-line blocking between channels 
• Descriptor overlap: the next node's reads start while the current node's writes drain (2 cycles between  nodes) 
• Dedicated descriptor manager with optional descriptor status write-back into each node 
• Up to 16 outstanding reads and 16 outstanding writes per channel; burst lengths computed a cycle ahead, off the arbitration path 

AXI5 Throughput Features 

• Unique ID indicator: every burst takes its own ID from a per-channel pool (1 to 16, default 8) and asserts  AxIDUNQ - the interconnect needs no ordering tracking for it 
• Out-of-order completion: one channel's reads and writes complete in any order; data is reordered in a slot  buffer and completion is counted per descriptor 
• Read data chunking: memory returns wide reads in 128-bit chunks in any order; each chunk is written  straight into its buffer slot 
• Busy indicator: the outstanding-transaction limit steps down with RBUSY / BBUSY (75 / 50 / 25 %) and  recovers after a hold-off 
• QoS Accept: the round-robin arbiter favors requests the subordinate will accept now 
• Max_Transaction_Bytes: bursts are cut at the interconnect stripe size (64 to 4096 bytes), so the  interconnect never splits them 
• Wake-up: AWAKEUP is raised a cycle before the first request after idle 

AXI5 Transactions 

• WriteZero zero fill per node: no source read and no write data on the bus 
• WriteNoSnoopFull: full-line, all-strobe writes let a system cache allocate without merging 
• Prefetch: optional data-less hint issued ahead of the read stream to hide DRAM latency 
• Regular-transactions-only build for interconnects that require it 

System, Integrity and Control 

• Per-channel ARCACHE / AWCACHE and ARPROT / AWPROT: bufferable writes allow early  responses; no-allocate reads keep source data out of the system cache 
• Data Check: odd parity per byte on read and write data (RDATACHK / WDATACHK) 
• AXI5-Lite register subordinate with WSTRB; 32-bit, 4 KB register window 
• Descriptor-level error reporting: failing node address and cause (write response, read data or descriptor  fetch; SLVERR or DECERR) 
• Per-channel status and interrupts, global interrupt status / mask / vector, one processor interrupt; CIR and 
• CFR describe the build to software 
• Scatter-Gather and Transfer Control 
• Linked lists of 32-byte nodes with 64-bit addresses and a 24-bit length; chained and ring structures (start /  branch, re-start, Wait-On-Restart) 
• Memory-to-Memory, Memory-to-Peripheral, Peripheral-to-Memory, Peripheral-to-Peripheral; fixed address FIFO transfers; per-channel DREQ / DACK hardware pacing 
• Unaligned source and destination at any byte, any length

Integration 

• 1 to 126 channels (one global interrupt bank per 32); data width 64 / 128 / 256 / 512 / 1024 bits; 64-bit  addressing 
• Each AXI5 feature is a build or register option, declared through the AXI5 interface properties; with all off  the core is the DB-DMAC-MCn-AXI4-HT 
• SystemVerilog interfaces with modports plus a flat-pin wrapper; AMBA Manager / Subordinate naming 
• Fully synchronous single clock, rising-edge, no gated clocks, no internal tri-states; technology independent RTL for ASIC and FPGA 

• Bulk data movement on AXI5 network-on-chip and mesh interconnects with DDR or HBM memory 
• Wide 512 and 1024-bit data paths where read latency dominates 
• Buffer initialization and zero fill without a source read 
• Scatter-gather DMA for networking, storage and PCIe endpoint data movement