Digital Blocks is a leading developer of silicon-proven semiconductor Intellectual Property (IP) cores for developers requiring best-in-class IP for AMBA Peripheral such as Multi-Channel DMA / I3C / I2C / xSPI / eSPI Controllers, LCD / OLED Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines, LVDS Display Link Layer Drivers, Video Signal & Image Processing, and Low-Latency UDP & RTP Hardware Protocol Stacks.
We offer synthesizable RTL Verilog & SystemVerilog IP Cores for System-on-Chip (SoC) ASSP, ASIC, and FPGA designers. At Digital Blocks we are both System Architects and ASIC/FPGA designers. Thus, we provide IP Cores with deep system-level capabilities.
Building on our IP cores, Digital Blocks design services can customize the IP core to your unique requirements.
Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Int…
Display Controller – LCD / OLED Panels (Avalon Bus)
The DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus within Altera Qs…
RTP/UDP/IP Protocol Hardware Stack – H.264/H.265 NAL Video Streams Packet Processing
The DB-RTP-UDP-IP-NAL Intellectual Property Core is an RTP/UDP/IP Protocol Hardware Stack with the following protocol processing …
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…
AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI…
I2C Controller IP – Slave, Parameterized FIFO, AHB Master Interface (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, AXI Master Interface (I2C2AXI)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I2C Controller IP – Slave, Parameterized FIFO, APB Master Interface (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring intern…
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
The DB-I3C-BASIC-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI …
UDP/IP – 1 GbE Protocol Hardware Stack
The DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 1 GbE…
UDP/IP – 10 GbE Protocol Hardware Stack
The DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 10 G…
UDP/IP – 25 GbE Protocol Hardware Stack
The DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 25 G…
UDP/IP – 40 GbE Protocol Hardware Stack
The DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 40 &…
UDP/IP – 50 GbE Protocol Hardware Stack
The DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 50 G…
The DB-SPI-XIP-FLASH-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad…
I3C Controller IP- Slave, Parameterized FIFO, APB Bus
The DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
I3C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – I…
AXI4-Stream to/from AXI Memory Map - AXI Memory Map Conversion to AXI4-Stream, 16 Channels
The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the a…
AXI4-Stream to/from AXI Memory Map - AXI4-Stream Conversion to AXI Memory Map, 16 Channels
The DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to …
I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus
The DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – …