Vendor: Digital Blocks, Inc. Category: DMA

Fixed-Channel Multi-Channel DMA Controller

Scatter-Gather | AMBA AXI4 | 2, 4, 8 or 16 Channels

Overview

The Digital Blocks DB-DMAC-MCn-AXI4 SystemVerilog RTL IP Core is a Scatter-Gather (SG) Direct Memory Access (DMA) Controller for AMBA AXI4 systems with a fixed number of independent DMA Channels, 2, 4, 8 or 16 (MC2, MC4, MC8, MC16), and a DMA data path of 64, 128 or 256 bits. It is the fixed channel member of the DB-DMAC-MC-AMBA family, at a lower license cost: the data engine, register model, descriptor format and drivers of the configurable DB-DMAC-MCn-AXI4 and the high-throughput DB-DMAC MCn-AXI4-HT.

Each channel runs linked lists of descriptor nodes with 64-bit addresses, any byte alignment and up to 16 MB per node, with read and write bursts of 4, 8, 16 or a programmed 1 to 256 beats and up to 16 requests outstanding. One AXI4 Manager port carries the descriptor fetches and the DMA data of every channel. Measured at 128 bits, two channels use 86.7 % of the bus and one channel with programmed 32-beat bursts 85.3 %.

Key features

AXI4 Data Engine 

  • Programmable bursts: read and write bursts of 4, 8 or 16 beats, or a programmed 1 to 256 beats per channel (MCn MB-AXI4); INCR or FIXED addressing 
  • Outstanding requests: 1, 2, 4, 8 or 16 reads and writes outstanding per channel, bounded by the per-channel data  FIFO (see the TRM) 
  • Data FIFO: 256 words of the data width per channel, with a byte realigner between the read and the write side 
  • Round-robin channel arbitration with an O(log N) parallel-prefix select on each AXI4 Manager; per-channel ARQOS / AWQOS, descriptor fetches at ARQOS 0xF 

Descriptor Processing 

  • Descriptor nodes are fetched over m_axi, one 256-bit read per node (4 beats at 64 bits, 1 beat at 256 bits) 
  • Per-channel pre-fetch of up to 32 descriptor nodes ahead of execution 
  • Descriptor list start / branch (DLB) and re-start (DLR) at any time 

Scatter-Gather and Transfer Control 

  • Linked lists of 32-byte descriptor nodes: 64-bit source, destination and next address, 24-bit byte length (1 byte to 16 MB per descriptor node) 
  • Chained and ring descriptor structures with the descriptor node's NAV, LDN and WOR flags 
  • Memory-to-Memory, Memory-to-Peripheral, Peripheral-to-Memory, Peripheral-to-Peripheral 
  • Unaligned source and destination addresses at any byte, any length (byte rotator, WSTRB on the first and last word);  automatic split at 4 KB boundaries 
  • Fixed-address (FIFO) reads and writes; hardware-paced bursts with per-channel DREQ / DACK pairs for reads and writes 
  • CPU software or external hardware initiated transfers 

Status, Interrupts and Error Handling 

  • Per-channel status: descriptor list and descriptor node complete, descriptor read, source read and destination write errors, data and descriptor parity errors, re-start failure - each with an interrupt mask; a masked error holds the  channel until cleared or reset 
  • Per-channel interrupt outputs; global interrupt status / mask / vector registers and one processor interrupt 
  • Event-safe write-1-to-clear: a hardware event in the same cycle as the clear is never lost 
  • Optional per-byte parity checking on data and descriptor reads; parity generated on writes 
  • Core Identification Register (CIR): vendor, channel count, address width, bus and revision 

Integration 

  • 2, 4, 8 or 16 channels (MC2 / MC4 / MC8 / MC16); data width 64 / 128 / 256 bits; 64-bit addressing. Both fixed per license 
  • SystemVerilog RTL with a flat-pin top level; AMBA AXI4 Manager / Subordinate naming 
  • Fully synchronous single clock, rising-edge, no gated clocks, no internal tri-states; technology-independent RTL for ASIC and FPGA 
  • Upgrade path: the configurable DB-DMAC-MCn-AXI4-Config (1 to 126 channels, up to 512 bits) and the High Throughput DB-DMAC-MCn-AXI4-HT keep the register model, descriptor format and drivers 

Block Diagram

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Applications

  • Memory-to-memory copy engines in SoCs 
  • Scatter-gather DMA for networking, storage and PCIe endpoint data movement 
  • Peripheral data streaming with hardware request / acknowledge pacing 
  • Offload of bulk memory copies from CPU clusters, under Linux or bare metal 

Specifications

Identity

Part Number
DB-DMAC-MCn-AXI4 Fixed
Vendor
Digital Blocks, Inc.
Type
Silicon IP

Files

Product Sheet Download

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Provider

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Frequently asked questions about DMA IP

What is Fixed-Channel Multi-Channel DMA Controller?

Fixed-Channel Multi-Channel DMA Controller is a DMA IP core from Digital Blocks, Inc. listed on Semi IP Hub.

How should engineers evaluate this DMA?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DMA IP.

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