Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
- Hash / MAC
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
Message Digest Algorithm Processor
The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores.
AES-CCM Authenticated Encrypt/Decrypt Engine
The AES-CCM encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
AES-GCM Authenticated Encrypt/Decrypt Engine
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Programmable Advanced Encryption Standard Engine
The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Encryption Standard.
The SHA-3 module implements the SHA3-512, SHA3-384, SHA3-256 and SHA3-224 hash algorithms and the SHAKE128 and SHAKE256 extendabl…
SHA-512, SHA-384, SHA512/256 and SHA-512/224
The SHA-512 module implements the SHA-512, SHA-384, SHA-512/256 and SHA-512/224 hash algorithms specified in FIPS PUB 180-4, the …
The SHA-256 module implements both the SHA-256 and SHA-224 hash algorithms specified in FIPS PUB 180-4, the Secure Hash Standard.
IEEE 802.1ae MACSEC IP Core for 10 Gbit Ethernet
Ethernet is a ubiquitous, efficient and cost-effective transport mechanism for unified communication of voice, data and video ove…
Multiple SecY IEEE 802.1ae MACSEC IP Core for 40Gbit Ethernet
Ethernet is a ubiquitous, efficient and cost-effective transport mechanism for unified communication of voice, data and video ove…
AES-GCM IP Core for 40Gbit/sec packet data
This state of the art implementation of AES-GCM achieves 40Gbit/sec performance on Virtex 5 FPGAs.
Duplex AES-GCM at 10Gbit/sec for OTN
This state of the art implementation of the AES-GCM algorithm provides privacy and authentication and achieves 10Gbit/sec perform…
This core extends the Algotronix G3 Encryption Standard (AES) core by providing a secure, standardized method for loading cryptog…
High speed low latency AES-GCM pipeline, 100Gbps
The AES-IP-61 (EIP-61) is IP for accelerating AES-GCM based cryptographic solutions.
TRNG fully compliant with NIST 800-22
The eSi-TRNG is a high quality implementation of a True Random Number Generator fully compliant with latest NIST 800-22.
Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration.
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies.
RSA Public Key Cryptography Exponentiation Accelerator
The modular exponentiation accelerator IPX-RSA is an efficient arithmetic coprocessor for the RSA public-key cryptosystem.
SMIC 0.18um Random Code Generator
SMIC18_RCG_02 is to generate random code.