LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption.
- AES
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption.
The Helion Modular Exponentiation core performs the Z = YE mod M computation which is at the heart of many commonly used Public-K…
High-Speed AES Encryption Cores
D’Crypt’s AES core is a high-performance pipelined implementation of the AES (Rijndael) encryption algorithm.
SHA-1 Hash Function Calculation
The ALSHA core is the VHDL model of the processor that performs SHA-1 hash function calculation.
DES Encryption and Decryption Processor
The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption.
PUF Hardware Premium with key wrap and certification support
Device identities and cryptographic root keys are at the foundation of every security system.
NIST’s ASCON Lightweight Crypto Algorithm Accelerator
The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON.
Agile PQC Public Key Accelerator
Quantum computers will solve some of the most complex problems in minutes versus the potentially thousands of years that classica…
HDCP 1.4/2.2/2.3
The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin …
TRNG (True Random Number Generator) NIST SP800-90C
TRNG Core meets NIST SP 800-90A/B standard It is the basis of the Root of Trust System, mainly it comes with other Security Eleme…
Silicon Proven Hardware Root of Trust
The Root of Trust (RoT) is always the trusted root within a cryptographic system.
Integrated Security Services Platform (iSSP)
Secure-IC offers the first worldwide PQC ready Security Lifecycle Management solution.
Background: Attacks on electronic devices and systems such as IOT endpoints, computers, medical devices and infrastructure are on…
ZUC (128-EEA3 and 128-EIA3) Core
This IP core implements the ZUC stream cipher and the 128-EEA3 encryption and 128-EIA3 authentication algorithms based on it whic…
This IP core implements the SHA-1, SHA-256, SHA-384 and SHA-512 algorithms specified in FIPS180-4 which are widely used for authe…
IPSEC (RFC 4303) 1Gbit IP Core
The IPSEC core is a high performance pipelined implementation of the Encapsulating Security Protocol mode of IPSEC (RFC4303) with…
GSMC18_RCG_03 is to generate random code with the sampling clock up to 250MHz.
This IP is specially designed for anti-tamper protection.
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.