Vendor: CAST Category: Hash / MAC

Message Digest Algorithm Processor

The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a varie…

Overview

The  MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. It computes a 120-bit message digest for messages of up to (264 – 1) bits.

The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

The MD5 core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs.

The MD5 core has been robustly verified and is silicon-proven.

Key features

  • RFC 1321 compliant
  • Suitable for data authentication applications
  • Maximum message length is 264 - 1
  • Simple, fully synchronous, reusable design
  • Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
  • Complete deliverables include test benches, C model and test vector generator

Block Diagram

Specifications

Identity

Part Number
MD5
Vendor
CAST
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

Learn more about Hash / MAC IP core

From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication

This article reviews the functional-safety attributes of Classical CAN and CAN FD, then explains how CAN XL preserves and extends them. It also discusses higher-layer safety protocols, fault-tolerant CAN XL controller implementations, and CANsec, the CAN XL security extension inspired by the MACsec model. Finally, it highlights how the CAST CAN XL controller IP and CANsec acceleration IP can support the efficient deployment of safety- and security-capable in-vehicle networks.

Time Sensitive Networking for Aerospace

This white paper highlights the integration of Time-Sensitive Networking (TSN) in the aerospace industry. It provides an overview of TSN standards and profiles and the IEEE P802.1DP standard relevant to aerospace applications. It also discusses key topics such as time synchronization, latency, resource management, and reliability in the context of TSN.

Frequently asked questions about Hash / MAC IP cores

What is Message Digest Algorithm Processor?

Message Digest Algorithm Processor is a Hash / MAC IP core from CAST listed on Semi IP Hub.

How should engineers evaluate this Hash / MAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP