The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrat…
- Security Coprocessor
- Available on request
- Available
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrat…
Common public key algorithms include RSA, Digital Signature Algorithm (DSA), and Diffie-Hellman (DH), which require the calculati…
128-bit Public Key Accelerator
Common public key algorithms include RSA, Digital Signature Algorithm (DSA), and Diffie-Hellman (DH), which require the calculati…
When safety & security meet the best size/performance ratio… ECDSA IP Core Elliptic curves form the foundation of cutting-edge pu…
Elliptic curves form the foundation of cutting-edge public-key cryptography, serving as a crucial component for secure digital si…
VISENGI's SHA-2 Secure Hash Algorithm IP core has been developed to be the highest throughput SHA-2 cryptographic hasher while at…
AES Authenticated Encryption Accelerator with DPA or with DPA and FIA
The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher accel…
DOME - Device Ownership Management and Enrollment
Everyday there are millions of devices that enter the IoT that contain a processor that must be maintained, monitored and securel…
Ironwood KAP (TM) Fast, Future-Proof Key Agreement Protocol Designed for Low-Resource Devices
Key agreement protocols are at the foundation of many of today's security applications.
The MVD DVB-CSA Descrambler core allows to decrypt MPEG-TS stream using ETSI specified DVB Common Scrambling Algorithm (CSA2).
600Mb/s Authentication IP Core for AXI-4 Streams Optimized for Area MD5 Stream Authentication IP Cores converts streams of data i…
Elliptic Curve Digital Signature generation and verification
eSi-ECDSA is a hardware acceleration core for Elliptic Curve (EC) Digital Signature Algorithm modular arithmetic operations defin…
Attack resistant ECC hardware acceleration core
eSi-ECC is a hardware acceleration core for Elliptic Curve (EC) modular arithmetic operations, which are commonly performed withi…
The CRYPT-IP-120 combines local key storage, an AES cipher (AES-IP-39), a SHA-2 hash (HASH-IP-57) and DMA capability into an easy…
Multi-2 Descrambler Supporting BCAS for ISDB-T,TMM in Japan
MEGACAST MULTI2 IP core implements the MULTI2 encryption/decryption algorithms as specified by ISO9979/0009 algorithm register en…
This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle.
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library.
This is a high performance pipelined implementation of AES optimized for encryption of uncompressed video on low cost FPGA famili…
This hardware IP core features a full Secure Hash Algorithm SHA1.
The MW_AES core performs the digital baseband function that can be used to protect electronic data.