AES-GCM Authenticated Encrypt/Decrypt Engine

The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. 

Four architectural versions are available to suit system requirements. The Standard version (AES-GCM-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-GCM-F) achieves higher throughput using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block depending on key size.

For applications where throughput is critical there are two additional versions. The High Throughput AES-GCM-X can process 128 bits/cycle and the Higher Throughput AES-GCM-X2 can process 256 bits/cycle respectively independent of the key size.

GCM stands for Galois Counter. GCM is a generic authenticate-and-encrypt block cipher mode. A Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt.  

• Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm 
• NIST-Validated
• Implemented according to the National Institute of Standards and Technology (NIST) Special Publication 800-38D
• Processes 128-bit data in 32-bit blocks
• Employs user-programmable key size of 128, 192, or 256 bits
• Any size IV length
• Easy integration & implementation
  • Works with a pre-expanded key or can integrate the optional key expansion function
  • Fully synchronous, uses only the rising clock-edge, single-clock domain, no false or multicycle timing paths, scan-ready, LINT-clean, reusable design
  • Simple input and output interface, optionally bridged to AMBA™ interfaces or integrated with a DMA engine.
• Available in VHDL or Verilog source code format, or as a targeted FPGA
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