Programmable Advanced Encryption Standard Engine

The AES-P encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. 

Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block.  It can be programmed to use any of the following cipher modes: CBC, CTR, ECB, and OFB. 

The core works with a pre-expanded key, or with optional key expansion logic. 

The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.  

• Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
• Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
• Processes 128-bit data in 32-bit blocks
• Employs user-programmable key size of 128, 192 or 256 bits
• Two architectural versions:
  • Standard is more compact: 32-bit data path size Processes each 128-bit data block in 44/52/60 clock cycles for 128/192/256-bit cipher keys, respectively
  • Fast yields higher transmission rates: 128-bit data path Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher keys, respectively
• Supports Cipher Block Chaining (CBC), Cipher Feedback (CFB), Counter (CTR), Electronic Codebook (ECB), and Output Feedback (OFB) modes
• Works with a pre-expended key or can integrate the optional key expansion function
• NIST-Validated
• Simple, fully synchronous, reusable design
• Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
• Complete deliverables include test benches, C model and test vector generator