This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
- V-By-One
- OpenLDI ,LVDS IEEE Standard…
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
This FPD-Link Transmitter Macro is based on National Semiconductor openLDI specification v0.95 dated May 13th 1999 that allow the…
The MVD Remultiplexer core analyses the MPEG TS stream inputs and gives access to the followings information and statistics : * I…
Lancero Scatter-Gather DMA Engine for PCI Express
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI …
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU,…
FPD-link, 30Bits Color LVDS Receiver, 150Mhz (SVGA/WXGA)
Now available up to 150Mhz (90Mhz previously) V-Trans 's FPD Link Receiver Macro is based on National Semiconductor openLDI speci…
Dual RSDS Transmitter, 24/18-bit color, 40-300Mb/s (SVGA/UXGA/full HDTV) LCD & Plasma display
This RSDS Transmitter interface IP is based on RSDS “Intra-Panel” Interface Specification rev1.0, dated May 2003 that allow the t…
1G TCP Offload Engine TOE Very Low Latency (TOE)
INT 1011 is flexible that is customizable for layer-3, layer-4, layer-5 network infrastructure and network security systems appli…
1G TCP Offload Engine TOE +PCIe Very Low Latency (TOE+PCIe)
INT 1012 is the only SOC that integrates 1G TOE + 1 GEMAC + PCIe/DMA + Host interfaces in the smallest logic footprint.
LVDS Receiver 1250Mb/s, 800Mhz clock
V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high …
LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
V-Trans 's LVDS technology solutions eliminate the trade-offs in speed, low power, low noise (EMI), and BOM cost saving for high …
The DUSB2 is hardware implementation of full/high-speed peripheral controller that interfaces to the UTMI bus transceiver.
General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple inp…
I2C Controller IP – Master, Parameterized FIFO, APB Bus
The DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
Video LVDS SerDes Transmitter-Receiver IP Core
The Video LVDS SerDes Transmitter / Receiver IP Core provides a , easy-to-use Serializer/Deserializer (SerDes) solution to interf…
The Beyond AC97 Audio Controller IP Core enables audio control for SoC and FPGA.
MAC 10/100/1000 Ethernet Controller
The Beyond MAC (Medium Access Control) 10/100/1000 Ethernet Controller consists of a synthesizable Verilog RTL core that provides…
Today, the PCI bus is the number-one device connectivity standard on the market to integrate modern embedded applications into bi…
XMAC core from Flowgic Inc.
Interlaken Communication Controller
Flowgic's Interlaken IP core is an efficient implementation of Interlaken Protocol version 1.1.