The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices.
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Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The IntelliProp IPC-GZ189A-DT Gen-Z Responder is an IP Core that allows the building of Gen-Z compliant media devices.
AXI Fabric Package for Scalable SoC Applications
AndeShape AE300 package in this document refers to two licensable Andes platform products, the AE300FB AXI fabric and the AE300EP…
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specif…
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as spe…
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller.
General Purpose Input/Output Controller
The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller.
Serial Front Panel Data Port (sFPDP) IP Core
The sFPDP core provides a IP solution for the VITA 17.1-2015 sFPDP specification.
Provides Time-Sensitive Networking (TSN) capabilities to devices that operate as end systems in the network
High speed analog circuits for USB3.0 PHY application 745um*620um
UART Serial Interface Controller
The CC-UART-AXI is a synthesisable Verilog model of a UART serial interface controller.
UART Serial Interface Controller
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-AXI is a synthesisable Verilog model of a I2C serial interface controller.
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller.
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller.
Multi-protocol time synchronization IP
Provides sub-microsecond time synchronization, ensuring maximum flexibility for every scenario
IRIG 200-04 compliant time synchronization slave / time receiver for FPGA
IRIGtimeM implements an IRIG 200-04 compliant time synchronization master on FPGA devices.
PTP ordinary (master / time transmitter & slave / time receiver) clock
Provides nanosecond level clock synchronized to network PTP time transmitter.
10M/100M/1G Managed Redundant Switch IP Core
HSR/PRP redundancy + Legacy ethernet ports