AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Mas…
- Bus Fabric
- Source Code Available Immediately
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Mas…
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA…
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
Configurable CAN Bus Controller IP with Flexible Data-Rate
The Controller Area Network (CAN) is widely used in automotive and industrial applications.
GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC
The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption.
The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC.
Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
USB 2.0 Device Controller with ULPI interface
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver.
Complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2
Compliant with both MIPI D-PHY version 1.2 and LVDS specifications that can be applied to OpenLDI V0.95
ISO 7816 based Smart Card Reader IP
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications.
MIPI M-PHY v3.1 IP, Silicon Proven in TSMC 28HPC+
The MIPI M-PHY Gear 3 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v3…
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 in…
10M/100M/1G Multiport TSN Ethernet Switch IP Core
Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities
VME System Controller with AXI4 user interface and 2eSST support
The VMESCmodule2 is Inicore's next generation VME System Controller core designed for FPGA and ASIC integrations.
VME System Controller with AXI4 compliant user interface
The VMESCmodule2 is Inicore's next generation VME System Controller core designed for FPGA and ASIC integrations.
The MVD Multi-RTP transmitter allows the transmission of several RTP streams on an Ethernet Network.
UDP Network Interface with Ethernet MAC for the M8051W & M8051EW
The UDPMAC implements a UDP transport layer, and IP layer functions, compatible with the RFC768 and RFC791 protocols.