Vendor: Rambus, Inc. Category: VESA DSC

VESA VDC-M Decoder

The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.

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Overview

The VESA DSC and VDC-M IP cores deliver visually lossless video compression for mobile, AR/VR and automotive display applications.

The VESA DSC IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image. The VDC-M cores use more sophisticated video encoding tools to achieve even higher compression factors for applications that require even more compression. VDC-M can reduce a 30 bpp uncompressed image to 6 bpp, and in some use cases, it can be visually lossless at a 6X compression ratio.

The VESA DSC and VDC-M IP cores can be combined with the MIPI DSI-2 Controller cores, and your choice of C/D-PHY, to form a complete display solution.  

Key features

  • VESA Display Compression-M (VDC-M) 1.2 compliant
  • Supports all VDC-M encoding mechanisms: BP, transform, MPP, MPP fallback, BP skip, flatness detection and signaling
  • Configurable maximum display resolution of up to 16Kx16K
  • Configurable compressed bit rate, in increments of 1/16 bpp
  • 8, 10, or 12 bits per component video
  • 4:4:4 sampling for RGB video input format
  • 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats
  • 2 pixel / clock (Encoder) and 4 pixels / clock (Decoder) internal processing architecture
  • Parameterizable number of parallel slice encoder instances (1,2, 4, or 8) to adapt to the capability of the technology and target display resolutions used
  • Supports logical slice encoding (soft slice) in each physical encoder (hard slice)
  • 100% verification coverage based on UVM environment
  • Verified against the VESA VDC-M 1.2.2 C model using a comprehensive test image library

Block Diagram

VESA VDC-M Decoder block diagram

Applications

  • Mobiles & Tablets
  • AR/VR Products
  • MIPI DSI-2 Applications
  • Automotive Video Transmission

What’s Included?

  • Encrypted RTL source code IP core
  • Functional and structural coverage reports
  • Comprehensive integration guide

Specifications

Identity

Part Number
VESA VDC-M Decoder
Vendor
Rambus, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA
Contact Rambus, Inc.

Learn more about VESA DSC IP core

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about VESA DSC IP cores

What is VESA VDC-M Decoder?

VESA VDC-M Decoder is a VESA DSC IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this VESA DSC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this VESA DSC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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