The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication …
- Video Transport
- Available for immediate sale
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication …
CSI2 TX; Camera Serial Interface, MIPI Compliant
CSI2 – TX is part of HCL’s MIPI® compliant offerings.
Camera/HDMI Video Input Interface
Camera/HDMI Video Input Interface core capture the incoming clocked video of horizontal and vertical active picture data and remo…
iWave's ARINC IP core is ARINC 818–compliant, which can be implemented on any transceiver based FPGA.
iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.
iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.
PCIe to ISA bride is a IP core which converts PCIe to ISA master bus interface.
PCIe to UART bridge is a IP core which converts PCIe to UART bus interface .
PCI Controller provides an interface between the PCI bus and user interface.
Common Public Radio Interface (CPRI) v.6.1 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
Fast, reliable connectivity in any FPGA using a minimum of FPGA resources The TCP/IP (Transmission Control Protocol/ Internet Pro…
The Microtronix Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfa…
The MVD RTP Receiver allows the reception and the processing of an RTP stream.
The MVD Multi-RTP transmitter allows the transmission of several RTP streams on an Ethernet Network.
This RTP Transmitter IP core implements a full Hardware RTP Transmitter.
High-availability Seamless Redundancy and Parallel Redundancy Protocol (HSR and PRP, IEC 62439-3 Clause 5 and 4 respectively) Edition 4.0 protocols
Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 …
SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (bot…
High Speed UART IP core - Universal Aysynchronous Receiver / Transmitter
The D2698 is a Octal UART Core software compatible with the SC2698.
Configurable UART with FIFO, software and hardware flow control
The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the OX16C950.