MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
- MIPI D-PHY
- TSMC
- 28nm
- HPC+
- In Production
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
MIPI D-PHY Tx IP, Silicon Proven in UMC 55LP
Version 1.2 of the D-PHY specification is completely complied with by the MIPI D-PHY Analog TX IP Core.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
This Peripheral Component Interconnect Express Gen3 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4.3 in…
10M/100M/1G Multiport TSN Ethernet Switch IP Core
Multi-port, multi-rate managed Ethernet switch with Time-Sensitive Networking (TSN) capabilities
VME System Controller with AXI4 user interface and 2eSST support
The VMESCmodule2 is Inicore's next generation VME System Controller core designed for FPGA and ASIC integrations.
VME System Controller with AXI4 compliant user interface
The VMESCmodule2 is Inicore's next generation VME System Controller core designed for FPGA and ASIC integrations.
The MVD Multi-RTP transmitter allows the transmission of several RTP streams on an Ethernet Network.
UDP Network Interface with Ethernet MAC for the M8051W & M8051EW
The UDPMAC implements a UDP transport layer, and IP layer functions, compatible with the RFC768 and RFC791 protocols.
The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication …
CSI2 TX; Camera Serial Interface, MIPI Compliant
CSI2 – TX is part of HCL’s MIPI® compliant offerings.
Camera/HDMI Video Input Interface
Camera/HDMI Video Input Interface core capture the incoming clocked video of horizontal and vertical active picture data and remo…
iWave's ARINC IP core is ARINC 818–compliant, which can be implemented on any transceiver based FPGA.
iW-SDIO to UART bridge is a IP core which converts SDIO slave to UART bus interface.
iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.
PCIe to ISA bride is a IP core which converts PCIe to ISA master bus interface.
PCIe to UART bridge is a IP core which converts PCIe to UART bus interface .
PCI Controller provides an interface between the PCI bus and user interface.
Common Public Radio Interface (CPRI) v.6.1 IPC
CPRI (Common Public Radio Interface) is an interfacing standard for high-speed communication of digital radio samples and control…
TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
Fast, reliable connectivity in any FPGA using a minimum of FPGA resources The TCP/IP (Transmission Control Protocol/ Internet Pro…
The Microtronix Camera Link Aligner IP Core is designed for building Frame Grabber (Receiver) Medium & Full Channel Link™ interfa…
The MVD RTP Receiver allows the reception and the processing of an RTP stream.