Highly flexible, low-latency, multiport TSN Ethernet switch
- Ethernet
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Highly flexible, low-latency, multiport TSN Ethernet switch
Multi-Protocol AMBA Support - Advanced Routing & Arbitration - Virtual Channel Deadlock Avoidance - Unlimited Scaling
The V-by-One VIP is fully compliant with the V-by-One standard. Supports THine V-by-One HS, HS Plus
The AXI-BRG enables communication between an AXI5 interface and an AXI4 interface.
AXI5-Stream to/from AXI4-Stream Bridges
The AXIS-BRG enables communication between an AXI5-Stream interface and an AXI4-Stream interface.
The APB-BRG enables communication between an APB5 Requester and an APB4 Completer.
The UALink IP supports 800Gbps and 400Gbps bandwidth modes with backward compatibility for 200Gbps and 100Gbps.
High-Performance AXI to UCIe FDI Interface IP for Scalable System Integration
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
Simplified Integration USB PD Capable Type-C Sink IP
Easy to integrate and configure Type-C sink port with Power Delivery. Delivered as RTL and an Analog Front End hard macro.
16 Gbps APXpress PHY with 4-tap Tx FIR, CTLE, 12-tap DFE, and 30 dB IL target. Part of the Inova APXpress ecosystem
Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development
Simplified Integration USB PD Capable Type-C Source IP
This OT9120 is an easy to integrate and configure Type-C source port with Power Delivery.
Ultra Ethernet MAC & PCS 100G/200G/400G/800G
Complete, silicon-agnostic implementation of the Ultra Ethernet Transport link layer
Ethernet PCS 100G/200G/400G/800G/1.6T
Silicon agnostic, highly configurable Ethernet PCS IP for Ultra High Speeds
Ethernet MAC 100G/200G/400G/800G/1.6T
Silicon agnostic, highly configurable Ethernet MAC IP for Ultra High Speeds
Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®
UCIe PHY IP with X16 data width for standard package and up to 8 Gbit/s per pin data rate
400G UDP/IP Hardware Protocol Stack
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.
Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…