100G TCP/IP Hardware Stack

The TCPIP-100G core implements a complete TCP/IP Hardware Protocol Stack capable of transmitting and receiving data at speeds up to 100 Gbps. More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from—or even the presence of—a system processor.

The core acts either as a server or a client, and it autonomously opens, maintains, and closes TCP connections without assistance from the host system. The system integrating the TCPIP-100G core can configure network parameters and preferences by accessing the core's control registers, and the core can then receive and send data via streaming data interfaces.

The highly configurable core can adapt to different applications and diverse system requirements. The maximum number of simultaneous TCP sessions is configurable at synthesis time; it can be as high as 32,768 for devices like data servers. Further user options include implementing a DHCP client that allows the core to automatically be assigned an IP address, enabling or disabling the reassembly of out-of-order TCP packet data, and integrating a UDP hardware stack with multicast support (IGMPv3).

Users can also choose either cut-through or store-and-forward packet processing mode. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets' integrity can be validated. This yields extremely low latency and requires less memory, but the core cannot reassemble out-of-order packets and it may deliver packet data that it will subsequently mark as invalid. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets, but will have higher latency and require more memory resources.

The TCPIP-100G core is rigorously verified and available in RTL source or as a targeted FPGA netlist. Its deliverables include a testbench, synthesis and simulation scripts, and comprehensive user documentation.

Fonctional Description

The TCPIP-100G core receives and transmits TCP packet data and forwards other traffic from the Ethernet MAC to the application and vice versa. It also receives and transmits ARP requests and responses, and responds to ICMP echo reply messages. The core can optionally also support the UDP and DHCP protocols.

The core consists of the following modules:

• Ethernet Module: Sends/receives Ethernet frames to/from an external Ethernet MAC, detects the frame type, and multiplexes frames between the protocol stack subsystems.
• VLAN Tx/Rx Module: Receives Ethernet frames from an external Ethernet MAC and, when enabled, detects and compares VLAN tags and filters frames to the correct VLAN tag. In the transmission direction, the module receives Ethernet frames from the Ethernet Frame module and adds the VLAN tag to the frames when enabled.
• ARP Module: Sends and receives ARP packets and handles them according to commands in each packet. It provides the IP-to-MAC address translation services to the IPv4 layers in the protocol stacks.
• IPv4 Module: Processes the received frames and distributes decoded frames to the related protocol stack modules. Frames from the upper protocol layers are encapsulated into the IPv4 frames and passed to the Ethernet module.
• TCP Module: Provides the primary functionality of the TCPIP-100G core, i.e. the TCP stack, fully implemented in hardware. The transmit and receive buffers are located in an external memory accessed via the AXI bus.
• ICMP Module: Supports the echo request response (ping).
• UDP Module: Is responsible for processing UDP packets for the DHCP module. The module can also provide user UDP channels to the user's design.
• IGMP Module: Adds the IGMP protocol stack needed for UDP multicast support. The module is optional and requires the user UDP channels feature to be enabled.
• DHCP Module: Automatically requests and acquires an IP address from a DHCP server. The DHCP feature is optional and requires the UDP module.
• Control and Status Registers: Control the core's functionality and report its status.

Complete TCP/IP Hardware Stack

• 100G Ethernet Transmit and Receive
• TCP server or client with up to 32K simultaneous TCP sessions
• Autonomous and highly efficient TCP connection establishment, maintenance and teardown, retransmission, flow and congestion control
• Optional out-of-order TCP packet reassembly
• Checksums generation and validation
• IPv4 support
• Jumbo and Super Jumbo Frames
• ARP with Cache, ICMP (Ping Reply), VLAN (IEEE 802.1Q)
• UDP, IGMP, and DHCP (optional)

Trouble-Free Operation

• Highly flexible thanks to run-time programmable options including:
  • Local MAC address, IP address, Gateway IP address, and IP subnet mask
  • IP Address & Port Filters
  • Retransmission timeouts, limits, and enable/disable of fast retransmission
  • Flow control and congestion control
  • Window sizes, MSS
• Non-TCP/UDP IP traffic is optionally forwarded to the system via a dedicated port

Easy SoC Integration

• Standardized AMBA^® interfaces:
  • 512-bit AXI4-Stream for packet data
  • 32-bit AXI4-Lite for CSR (APB3 optional)
  • 2048-bit AXI4 for external memory
• Separate clock domains for packet processing and CSR interfaces
• Independent of external memory type and controller, and from the Ethernet MAC or PHY
• Optionally pre-integrated with CAST or other third-party eMAC cores

Versions & Configuration Options

• Maximum number of simultaneous TCP sessions (up to 32K)
• Cut-through or store & forward processing

The TCPIP-100G core's 100 Gigabit throughput, low latency, and autonomous hardware TCP/IP processing make it ideally suited for AI and HPC clusters, cloud and hyperscale data centers, SmartNICs, network interface cards, network storage and NVMe-over-TCP systems, cybersecurity appliances, scientific data acquisition, telecommunications equipment, financial trading platforms, and other high-performance embedded networking applications.

• Synthesizable RTL or FPGA netlist
• Testbench & sample test cases
• UVM-based verification environment (optional)
• Simulation & synthesis scripts
• Documentation