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Vendor:
Digital Core Design
Category:
I2C / I3C
Slave I2C bus controller with FIFO
The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus.
Overview
The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as:
- a slave transmitter or
- slave receiver
depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:
- clock synchronization,
- arbitration,
- high-speed transmission mode.
The DI2CS supports all transmission speed modes:
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
DCD’s IP Core is a technology independent design and can be implemented in various process technologies.
- a slave transmitter or
- slave receiver
depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:
- clock synchronization,
- arbitration,
- high-speed transmission mode.
The DI2CS supports all transmission speed modes:
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
DCD’s IP Core is a technology independent design and can be implemented in various process technologies.
Key features
- Conforms to v.3.0 of the I2C specification
- Slave operation
- Slave transmitter
- Slave receiver
- Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Double buffering of RX/TX data
- Configurable RX and TX FIFOs up to 256 bytes each
- Configurable length of SCL, SDA lines glitch filtering
- Allows operation from a wide range of input clock frequencies
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Interrupt generation
- User-defined data setup time
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Benefits
- Getting a sillicon proven IP
- Rapid prototyping and time-to-market reduction
- Design risk elimination
- Development costs reduction
- Full customization
- Technological independence (VHDL and Verilog)
- Global sales network
- Professional service
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
What’s Included?
- HDL Source Code
- Testbench environment
- Automatic Simulation macros
- Tests with reference responses
- Synthesis scripts
- Technical documentation
- 12 months of technical support
Specifications
Identity
Part Number
DI2CS
Vendor
Digital Core Design
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Poland
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Frequently asked questions about I2C / I3C IP cores
What is Slave I2C bus controller with FIFO?
Slave I2C bus controller with FIFO is a I2C / I3C IP core from Digital Core Design listed on Semi IP Hub.
How should engineers evaluate this I2C / I3C?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.