UCIe IP Core

Universal Chiplet Interconnect Express — the open die-to-die interconnect standard enabling multi-vendor chiplet ecosystems, advanced 2.5D/3D packaging, and scalable disaggregated SoC designs.

UCIe (Universal Chiplet Interconnect Express) is the open industry standard for die-to-die connectivity, enabling chiplets from different vendors to communicate with consistent signaling and protocol semantics. Supported by Intel, AMD, ARM, Samsung, TSMC, and 80+ industry members, UCIe is the foundation of the emerging chiplet economy.

Xtremesilica's UCIe IP core delivers the complete PHY, D2D adapter, and protocol tunnel layers for both Advanced (wafer-level, interposer) and Standard (organic substrate) package formats, with PCIe Gen 5/6 and CXL tunneling.

Advanced & Standard PHY

• Both PHY variants: Advanced Package (16 TB/s/mm at 4 µm bump pitch for interposer/CoWoS) and Standard Package (2 TB/s/mm for organic substrate BoS).

Multi-Protocol Tunneling

• PCIe Gen 5/6 and CXL 2.0/3.0 protocol tunneling over the UCIe D2D link, enabling coherent accelerators and high-bandwidth die-to-die transfers.

D2D Adapter Layer

• Complete Die-to-Die adapter implementing the UCIe Stack including sideband, mainband, parameter exchange, and FDI/RDI interfaces for PHY portability.

Streaming Protocol

• Raw streaming mode for custom proprietary protocols, providing maximum bandwidth utilization without PCIe/CXL encapsulation overhead.

Multi-Die Fabric

• Support for more than two chiplets via UCIe switch fabric, enabling compute + memory + IO chiplet configurations in a single advanced package.

Built-in Test (BIST)

• Loopback, PRBS pattern testing, eye diagram monitoring, and lane margining — essential for die-level testing before advanced package assembly.

AI Training SoCs

• Connect compute, HBM, and IO chiplets in a single CoWoS package, achieving massive bandwidth at sub-2 ns latency.

CPU + GPU Chiplets

• Multi-vendor chiplet disaggregation: CPU from one foundry, GPU from another, combined with UCIe for interoperability.

HPC Processors

• Modular HPC processor design with compute, cache, and memory controller chiplets at different process nodes.

5G Baseband

• Modem baseband chiplet connected to RF analog chiplet, separating mixed-signal from digital design and manufacturing.

Automotive SoCs

• Safety-critical compute chiplet co-packaged with sensor fusion and AI inference chiplets for autonomous vehicles.

Cloud Custom Silicon

• Hyperscaler custom SoC disaggregated into domain-specific chiplets for flexible yield improvement and cost optimization.

SmartNIC Chiplets

• Network, crypto, and storage function chiplets integrated in one package with UCIe as the low-latency internal fabric.

Research Platforms

• Academic and industrial ASIC research platforms enabling chiplet interoperability validation across multiple fabrication runs.

PHY Implementation

• Advanced Package PHY (4 µm bump pitch)
• Standard Package PHY (25–55 µm)
• Foundry-specific PHY kit (TSMC/Samsung)
• BIST & eye monitor logic

D2D Adapter & Stack

• UCIe D2D adapter (sideband + mainband)
• PCIe Gen 5/6 tunnel module
• CXL 2.0/3.0 tunnel module
• FDI/RDI interface wrappers

Verification Suite

• UVM testbench with UCIe VIP
• Protocol compliance checks
• Multi-die system simulation
• Link training stress regression

Documentation

• Architecture specification
• PHY integration guide
• Packaging design rules
• Multi-chiplet system design guide