USB-C Power Delivery IP Core

The Bitec USB-C Power Delivery IP Core provides USB Type-C Port Controller (TCPC) functionality for FPGA and ASIC designs, implementing the USB-PD physical layer and lower protocol layer per the USB-IF TCPCI specification.

The Bitec USB-C Power Delivery IP Core is a USB Type-C Port Controller (TCPC) implementing the USB-PD physical layer and lower protocol layer as defined in the USB Type-C Port Controller Interface (TCPCI) specification. Its TCPCI-compliant register map is register-compatible with standalone TCPC devices, so it can be driven unmodified by industry-standard TCPM software stacks. USB Power Delivery is used by every class of USB Type-C product – power adapters, docks, monitors, DisplayPort Alt Mode sources and sinks, and USB4 ports – so the core is not limited to any one application.

The core implements the BMC physical layer on the CC wire (4b5b coding, CRC-32, packet framing and receive clock recovery) together with the hardware portion of the protocol layer: automatic GoodCRC generation and checking, message retransmission and TCPCI alert generation. It is delivered with a complete TCPM software stack – a port of the NXP USB-PD 3.0 stack with DisplayPort Alternate Mode support – plus example designs that negotiate power and carry DisplayPort over the USB Type-C connector. Combined with the Bitec DisplayPort IP core it provides a complete DisplayPort-over-USB-C solution.

Technology Support

Designed for ASIC and Intel FPGA implementation. The RTL is vendor-independent and is delivered with technology-abstraction libraries (generic/ASIC, Intel, AMD, Lattice, Microchip, Efinix) – contact Bitec for support on other technologies.

Evaluation Platform

The evaluation design runs on the Intel Arria 10 GX FPGA Development Kit fitted with the Bitec USB-C FMC evaluation daughter card. It instantiates two PD ports – a DFP attached as Source and a UFP attached as Sink – negotiates power, enters DisplayPort Alternate Mode and carries DisplayPort (up to UHBR10) over the USB Type-C connector, with HPD transported in PD messages. A Cyclone 10 GX example design is also provided.

• USB Type-C Port Controller (TCPC) per the TCPCI specification
• Source, Sink or Dual-Role-Power operation (synthesis parameter)
• DFP and UFP data roles
• BMC physical layer on the CC wire: 4b5b coding, CRC-32, packet framing, receive clock recovery
• Hardware GoodCRC generation/checking, message retransmission and alert generation
• Cable attach/detach handling and plug-orientation detection
• VBUS detection (Sink) and VBUS enable control (Source)
• Rp termination options: Default, 1.5 A and 3.0 A
• 256-byte transmit and receive message buffers
• TCPCI register map accessible over APB or I2C
• HPD-over-PD signalling for DisplayPort Alternate Mode
• Intel Platform Designer (Qsys) component included

• Source, Sink and Dual-Role-Power (DRP) operation
• DFP and UFP data roles with DisplayPort Alternate Mode entry
• Register-compatible with standalone TCPC devices – works with industry-standard TCPM software stacks
• Complete TCPM software stack included (NXP USB-PD 3.0 port)
• Cable attach/detach handling, plug-orientation detection, VBUS detection and control
• Evaluation design available for the Bitec USB-C FMC daughter card

• Verilog RTL source code
• Intel Platform Designer (Qsys) component
• SystemVerilog testbench with simulation scripts
• TCPM software: NXP USB-PD 3.0 stack port with DisplayPort Alternate Mode
• Example designs for Intel Arria 10 and Cyclone 10 GX
• Reference Manual and USB-C PD / DP Alt Mode Application Note