USB OTG 2.0 with xHCI Verification IP

Truechip's USB OTG 2.0 Verification IP provides an effective & efficient way to verify the components supporting USB2 Revision 2.0 Specification. Truechip's USB OTG 2.0 is a Dual-Role Device controller, which supports both device and host functions and is fully compliant with OTG Supplement to USB2.0 specification, and supports high-speed (480Mbps), full-speed (12Mbps), low-speed (1.5Mbps) transfer. This VIP is a lightweight with an easy plug-and-play interface, so that there is no hit on the design cycle time.

• Operates in High-Speed and Full-Speed mode
• Support 9 channels in host mode
• 9 Device mode endpoints in addition to control endpoint 0, 4 in, 3 out and 2 IN/OUT
• Built-in one 1024x35 bits FIFO
• Internal DMA with scatter/gather function
• Supports packet-based, dynamic FIFO memory allocation for endpoints for flexible, efficient use of RAM
• Support dynamic FIFO sizing
• Supports all USB2 transfer types; Control, Bulk, Interrupt, Isochronous.
• Supports High Bandwidth ISO and Interrupt transfers.
• Supports automatic ping capability
• Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP)
• Supports suspend, resume, and remote wake
• Configurable Utmi+ Interface width 8 and 16 bits.
• Supports Randomization for packet fields and data payload with or without error injection.
• Comprehensive Compliance Test Suite for verification.
• Supports all types of error injection (control transfer error injection(Request error), PID, CRC, Interpacket Delay, Sync, EOP, Bitstuff etc.) and detection.
• Supports detailed activity log file for individual layers for ease of Debugging.
• Supports dynamically configurable modes.
• Strong Protocol Monitor with real time exhaustive programmable checks.
• Supports to configure Protocol Timers and intentional error masking.
• On the fly protocol checking using protocol check functions, assertion checks for UTMI and ULPI Interface.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Host & Device.
• Graphical analyser to show transactions for easy debugging.

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog
• Unique development methodology to ensure highest levels of quality
• 24X5 customer support & response under 90 Min.
• Unique and customizable licensing models.
• Exhaustive set of assertions and cover points with connectivity example for all the components.
• Consistency of interface, installation, operation and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment.

• USB2.0 HOST/DEVICE BFMs
• USB 2.0 Bus Monitor, Protocol Monitor and Scoreboard.
• BFM Agents for :
  • Protocol Layer
  • OTG Compliant PHY Layer
• Compliance Test Suite (CTS)
• Stress test for each standard layer
• xHCI VIP compatible with Revision 1.2
• Integration Guide, User Manual and Release Notes
• GUI analyser to view simulation packet flow