Arasan to demonstrate the industry's first MIPI SWI3S™ IP at the MIPI Member meet in Taipei
Arasan provides a Total SWI3S™ IP Solution including the SWI3S™ PHY which will be available on multiple foundry nodes 22nm and below.
Vendor:
Arasan Chip Systems Inc.
Category:
USB
eUSB2V2.0 Controller + PHY IP
Arasan Chip Systems, the provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 V2.0 IP.
Overview
Arasan Chip Systems, the leading provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 V2.0 IP. eUSB2 V2.0 is a new generation specification proposed by USB Association. While traditional eUSB2 meets basic connectivity needs at 480 Mbps, modern SoCs and peripherals demand significantly higher throughput. eUSB2-V2.0 bridges this gap by delivering up to 10× performance improvement, along with better power efficiency and EMI control — without changing the fundamental USB 2.0 software ecosystem.
eUSB2V2 supports data rates of up to 4.8 Gbps, with flexible configuration options for asymmetrical and symmetrical links, enabling designers to build highly efficient systems tailored to specific application needs.
Block Diagram
eUSB2V2.0 Controller + PHY IP block diagram
Specifications
Identity
Part Number
eUSB2V2.0 Controller + PHY IP
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about USB IP core
Arasan furthers MIPI I3C® compliance with its participation at the I3C® interop in Taipei
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Frequently asked questions about USB IP cores
What is eUSB2V2.0 Controller + PHY IP?
eUSB2V2.0 Controller + PHY IP is a USB IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.