SpaceFibre IP core
The SpaceFibre IP core supports up to 8 lanes.
Overview
The SpaceFibre IP core supports up to 8 lanes. On the Microchip SmartFusion2 the bit rate is the maximum allowed by the device, 2Gpbs per lane (16 Gbps). In the case of the Xilinx Zynq UltraScale+ this rate is 8Gbps per lane (64Gbps total). This IP core comes in 3 different versions. The first one is presented to the processor as a peripheral (AXI/AHB), the second one is a "bare metal" implementation that can be connected to any HDL design without any processor involved or maximum bitrate is needed. The last one is a bus extensor MMAP custom implementation on top of SpaceFibre. For the peripheral flavor, Linux support is available for transmitting raw frames or present it to the OS as a networking interface, supporting TCP/IP.
SPECIFICATIONS
| End of packet | Yes |
| Virtual channels | No |
| Multilane | 1 to 8 |
| Bitrate | 2 Gbps (SF2) 8 Gbps (ZynqMP) |
| Packet retransmission on error | Optional |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Spacewire IP core
Time Sensitive Networking for Aerospace
Frequently asked questions about SpaceWire IP cores
What is SpaceFibre IP core?
SpaceFibre IP core is a Spacewire IP core from Novo Space listed on Semi IP Hub.
How should engineers evaluate this Spacewire?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Spacewire IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.