Verification IP for eUSB 2 v2 and USB 2.0
Specifications: eusb2v2 rev0.9, USB 2.0 Interfaces: UTMI/ULPI/Serial/HSIC/EUSB2 (V1 & V2) DUT Types/Topology USB 2.0 - Host, Dev…
Overview
Specifications: eusb2v2 rev0.9, USB 2.0
Interfaces: UTMI/ULPI/Serial/HSIC/EUSB2 (V1 & V2)
DUT Types/Topology
- USB 2.0 - Host, Device, PHY and HUB
- EUSB2.0 - Repeater, Native Controller and PHY
Key VIP Features
- Specification linked Functional coverages
- Scoreboard, callbacks and error injection
- Speed modes - HS/FS/LS
Debug and Analysis
- Verdi based protocol and performance analysis
- Protocol checks at each layer
- Debug ports and trace files
Key Protocol Features
- Protocol Layer Features
- All transfer types (Ctrl, Bulk, intr, Iso & Split transfers)
- High bandwidth Iso/Interrupt transfers, Interleaving transfers/Ping transfers
- Different handshaking response (NAK/NYET/STALL/Nohandshake(timeout))
- Device framework transfer initiation
- PL Exceptions and error injections in packets (CRC16/5 error/Invalid PID/NPID/packet field errors, timeout)
- Link Layer Features
- All state machines entry/exit, Power mgmt. state entry/exit(L1/L2)
- Vbus cut off in-between transfers & during suspend
- Disconnect/connect during transfers & during reset, protocol reset in-between transfers
- Fslsserialmode/Test mode support
- OTG-SRP/HNP/ADP
- PHY Features
- Physical Exception and error injections(invalid SYNC and EOP, Bit-stuff error, Rxerror scenarios etc…)
- Sync/EOP length adjustment, Preamble mode support
- Keep alive(HS/LS) support
Test Suites / Groups Features
- Host/Device/HUB/PHY/XHCI
- AHB/AXI bus interface support along with system memory and backdoor
- Multi-controller and Multi-port support
- Tailor Made for Testbench Migration from IP level to SoC level
- Includes the Application Layer
Block Diagram
Specifications
Identity
Standards & Interfaces
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about USB IP core
New USB 80Gbps Specification Boosts Data Rate, Enables Four Protocols on One Bus
USB 3.2: A USB Type-C Challenge for SoC Designers
USB Dual Role replaces USB On-The-Go
The Universe's first mobile phone with USB Type-C and DisplayPort
Overcoming USB Type-C Verification Challenges
Frequently asked questions about USB IP cores
What is Verification IP for eUSB 2 v2 and USB 2.0?
Verification IP for eUSB 2 v2 and USB 2.0 is a USB IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.