Learn more about Single-Protocol PHY IP core
The 12-bit, 125Msps SAR ADC IPs deliver an ENOB ≥ 10.5 bit, SFDR ≥ 82.5 dB, and THD≤ ‑77.2 dB. Featuring a differential input design with high common-mode rejection ratio (CMRR), the IPs achieve an excellent anti‑interference performance, enabling precise capture of high-speed communication signals and reduced system bit error rates to meet signal acquisition requirements of communication transceivers.
By outstanding static and dynamic performance as well as high flexibility, this IP offers a mature, mass-production-ready solution for industrial control, high-end instrumentation, automotive electronics and other fields. It has been deployed in real-time digital signal processing for various customer products, proving its high reliability and manufacturability.
The PHY IP complies with PCIe 4.0 specifications, supports PIPE 4.4.1/5.2 interface and data transmission rates ranging from 2.5Gbps to 16Gbps, fully covering PCIe Gen4.0/3.0/2.0/1.0 standards, and is compatible with other protocols, such as Rapid IO, JESD204B/C, USB3.2/3.1/3.0, and 10GBASE-R/KR.
This IP has the features of high frequency and low power consumption. With the increasing demand for efficient lookup in network devices, such as fast processing of routing tables and Access Control Lists (ACLs), this IP will be widely adopted in chips for high-end switches, routers, etc.
Brite Semiconductor today announced the launch of DDR3/4, LPDDR3/4 Combo IP. Developed on 28HKD 0.9V/2.5V platform, this IP has extensive protocol compatibility, supporting DDR3, DDR3L, DDR4 and LPDDR3, LPDDR4 protocols. It achieves data transfer rates up to 2667Mbps and supports multiple data width configurations, including X16, X32, and X64.
Brite Semiconductor today announced providing MIPI IP total solution for custom ASIC/SoC design service. This solution consists of a series of MIPI controller and PHY. It will help the System Manufacturer and IC companies to design high quality ASIC/SoC products while speeding up time to market.
