32-bit/33MHz PCI Host Bridge

This PCI Host Bridge IP core enables data transfers between a host processor and PCI bus based devices. 

The bridge allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.

The core complies with the PCI bus specification versions 3.0 and 2.3, and can act as a PCI master and target. Furthermore, it implements PCI bus arbitration, supporting up to seven PCI bus agents, PCI reset signal generation, and all types of PCI transactions provisioned by the standard. 

The PCI-HB builds on more than 15 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.

• PCI Host Bridge
  • Enables data communication between the Host Processor and devices on the PCI bus
  • PCI I/O space and memory space are mapped directly to the host-bus memory space
  • PCI Interrupt and System Errors are propagated as interrupts to the host
  • PCI Configuration registers are accessible from both PCI and host directions
  • Asynchronous host and PCI clocks
• PCI Interface 
  • PCI specification 3.0 and 2.3 compliant
    • 33 MHz 
    • 32-bit bus width
    • 32-bit address space
    • Parity generation and parity error detection
  • PCI Master & Target support all types of transactions:
    • Configuration space read/write
    • Memory space read/write
    • I/O Space read/write
    • Interrupt acknowledge (optional)
    • Special cycles (optional)
  • PCI reset generator
  • PCI bus arbiter 
    • Up to 7 external bus agents
    • Flexible priority schemes
    • Agent malfunction detection and reporting