Vendor: Cadence Design Systems, Inc. Category: USB

USB 3.x Controller

Mature solution featuring xHCI Host, Device, and Dual-Role

Overview

Mature solution featuring xHCI Host, Device, and Dual-Role

The Controller IP for USB 3.1/3.0 offerings include xHCI Host (3.0), Device (3.0/3.1), and Dual-Role Device (3.0/3.1) controllers. USB 3.0 IP from Cadence was one of the first to receive a certification for compliance with the USB 3.0 specification from USB-IF.

Key features

  • Full Link Power Management (U0, U1, U2, and U3) with LFPS support
  • Up to 15 IN and 15 OUT configurable endpoints
  • Power and clock gating feature support
  • Multi-channel Scatter/Gather DMA with TRB caching
  • AXI features 128-bit datapath width and 64-bit address width

Block Diagram

Specifications

Identity

Part Number
USB 3.x Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

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Provider

Learn more about USB IP core

Securing the Most Important Goal of USB Type-C Technology: A Better User Experience

Now that the USB Type-C™ Cable and Connector Specification is starting to reach the masses, the world of advanced technology and hundred-pages-thick specifications finally meets the world of casual users. The initial impression is that while device owners appreciate the new features and ease of use, they are more puzzled than before with incompatibility of devices, dangerously bad cables, and the need for adapters for their old devices. What do we, as an industry, need to do to overcome these fears and secure a path to USB Type-C success?

Frequently asked questions about USB IP cores

What is USB 3.x Controller?

USB 3.x Controller is a USB IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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