The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications.
- BOW
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications.
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.
MSquare's eDP PHY is a reliable solution for display interface requirements, supporting resolutions of 4K and higher.
MSquare's ONFI 5.1 PHY is a high-performance and low-power PHY IP, which supports all modes of the Open NAND Flash Interface (ONF…
MIPI C/D Combo TX PHY and DSI controller
The MIPI C and D Combo Transmitter PHY and DSI Controller are tailored for high-performance display applications.
MIPI D-PHY TX PHY and DSI controller
The MIPI D-PHY Transmitter PHY and DSI Controller are tailored for high-performance display applications.
Our LVDS (Low Voltage Differential Signaling) and OpenLDI (Open Low-voltage Differential Signaling Interface) PHY which is compos…
The HDMI 2.0 TX (Transmitter) is a multimedia interface designed to deliver high-definition video and audio from source devices t…
The Embedded DisplayPort (eDP) 1.3 Transmitter PHY is a high-performance interface IP designed to enable the transmission of vide…
MIPI CD PHY Combo TX & RX + DSI & CSI Controller
Our MIPI CD-PHY Transmitter and receiver PHY with Display Serial Interface (DSI) and Camera Serial Interface (CSI) Controllers ar…
MIPI D-PHY TX & RX + DSI & CSI Controllers
Our MIPI D-PHY Transmitter and receiver PHY with Display Serial Interface (DSI) and Camera Serial Interface (CSI) Controllers are…
Our mass production-proven IPTD2D-A D2D Interconnect IP Solutions offer industry- power efficiency, performance, and low latency,…
The UCIe-S 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
Low Latency Ethernet 10G/25G MAC
The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to commmercialize and market HHI’s proven network technolo…
L2 cache option for multicore versions of ARC HS36 and HS38 processors
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…