The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug In…
- Verification IP
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol which is part of the Arm® Debug In…
Simulation VIP for AMBA Stream
Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI4-Stream specification which is part of the Arm® AMB…
Best-in-class Arm® AMBA® LTI Verification IP (VIP) for your IP, SoC, and system-level design testing.Cadence provides a mature an…
Cadence provides a mature and comprehensive Verification IP (VIP) for the LPI specification which is part of the Arm® AMBA® famil…
Cadence provides a mature and comprehensive Verification IP (VIP)for theDistributed Translation Interface (DTI) specification, wh…
Cadence provides a mature and comprehensive Verification IP (VIP) for the CXS specification which is part of the Arm® AMBA® famil…
Best-in-class Arm® AMBA® CHI Verification IP (VIP) for your IP, SoC, and System-level Design Testing Cadence provides a mature an…
Cadence provides a mature and comprehensive Verification IP (VIP) for the AXI specification which is part of the Arm® AMBA® famil…
Cadence provides a comprehensive solution to address Arm® AMBA® Adaptive Traffic Profiles (ATP) specification.
Cadence provides a mature and comprehensive Verification IP (VIP) for the Peripheral Bus (APB) specification, which is part of th…
Cadence provides a mature and comprehensive Verification IP (VIP) for the AHB specification which is part of the Arm® AMBA® famil…
Cadence provides a mature and comprehensive Verification IP (VIP) for the ACE specification which is part of the Arm® AMBA® famil…
The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for hi…
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge.
Octal SPI Master/Slave Controller
Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate eithe…
General-Purpose I/O Controller with APB Interface
The GPIO-APB core is used to create functions in a system that are not implemented with dedicated controllers, and require simple…
ITU-R BT.1120 Decoder – HD 1920x1080p
The DB1845 ITU-R BT.1120 / BT.656 Decoder IP Core decodes ITU-R BT.1120 and BT.656 digital video uncompressed NTSC and PAL video,…