Cadence Signs EuroCDP Agreement to Support European Chip Innovation
Agreement with the European Chips Joint Undertaking extends access to Cadence EDA and Systems technologies and Managed Cloud Service for eligible European startups and SMEs.
Vendor:
Cadence Design Systems, Inc.
Category:
Protocol Bridge
Simulation VIP for AMBA LTI
Best-in-class Arm® AMBA® LTI Verification IP (VIP) for your IP, SoC, and system-level design testing.Cadence provides a mature an…
Overview
Best-in-class Arm® AMBA® LTI Verification IP (VIP) for your IP, SoC, and system-level design testing.
Cadence provides a mature and comprehensive Verification IP (VIP) for the LTI specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence Verification IP for LTI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides Interconnect Validator connection for interconnect verification that verifies the correctness and completeness of data as it passes through the SoC. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for LTI helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: AMBA® LTI Protocol Specification (Includes both Issue A and Issue B spec)
Key features
- Supports LTI-A and LTI-B spec version
- LTI active and passive VIP supports both the specification version LTI-A and LTI-B.
- Channels
- Drive, sample, and check the signals and operations on LTI Request, Response, and Completion channels.
- Interface management support
- LTI active VIP does interface automatically and provides API for user-based control too. VIP also provides callback events to notify the change in the states.
- Credit Exchange based flow control
- LTI VIP does credit exchange flow control automatically and can enable user-based credit exchange control. Allowed to send user configurable maximum credit.
- Multiple VC support
- LTI VIP supports Multiple VC to send translation request.
- Out of Order response
- Translation response can be generated out of order by Active LTI Subordinate VIP and Passive mode can keep track of out-of-order responses.
- Automatic Response
- LTI Subordinate VIP is capable of generating a default response automatically. You can also modify it based on your requirement.
- Support for LTI_MMU and LTI_GPC enabled request
- LTI VIP supports a feature to enable MMU and GPC support for LTI-B version.
Block Diagram
Simulation VIP for AMBA LTI block diagram
Specifications
Identity
Part Number
Simulation VIP for AMBA LTI
Vendor
Cadence Design Systems, Inc.
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Protocol Bridge IP core
TDISP and Confidential Computing: Extending the PCIe Chain of Trust
This blog post examines how the TEE Device Interface Security Protocol (TDISP) enables trusted device assignment and works with Integrity and Data Encryption (IDE) in systems implementing the Arm Confidential Compute Architecture (CCA).
Cadence Expands Sovereign AI in Europe: From Chips to AI Factories
To bring computing scale and regional data control together, Cadence is expanding its sovereign AI data center in Munich, becoming the first electronic design automation (EDA)opens in a new tab vendor to deliver a comprehensive sovereign AI platform for semiconductor, system, and AI factory design in Europe.
PCI Express Security and TEE Integration, Part 2 - Protecting PCIe Traffic
This blog examines how Integrity and Data Encryption (IDE) secures PCIe traffic, including the roles of link IDE and selective IDE in direct-attached and switched topologies.
The Memory Challenge of Physical AI
As physical AI workloads become more complex, architects must now consider how predictably the complete system performs when multiple real-world workloads are active simultaneously.
Cadence Joins the Genesis Mission Consortium to Advance AI-Driven Scientific Discovery and Microelectronics Innovation
Cadence will bring AI-enabled electronic design automation, system design and analysis, and digital twin expertise to the DOE's AI-driven science initiative
Frequently asked questions about Protocol Bridge IP cores
What is Simulation VIP for AMBA LTI?
Simulation VIP for AMBA LTI is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.