The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
- UCIe
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects betwee…
Low Latency Ethernet 10G/25G MAC
The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to commmercialize and market HHI’s proven network technolo…
L2 cache option for multicore versions of ARC HS36 and HS38 processors
The ARC® HS3x processors, which include the HS34, HS36 and HS38, are based on the -efficient ARCv2 instruction set architecture (…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-d…
The high-quality, silicon-proven USB 1.1 Controller IP enables designers to implement a host and/or device into their SoC designs.
USB 1.1 Device Controller version 4 with Active Clock Gating to save active power
The high-quality, silicon-proven USB 1.1 Controller IP enables designers to implement a host and/or device into their SoC designs.
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 Host Controller Multiport
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
The vendor provides designers with silicon-proven, configurable USB 2.0 Controllers that are compliant with the USB-Implementers …
USB 2.0 nanoPHY - UMC 65SP, OTG
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 picoPHY - UMC 28HLP18 x1, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 femtoPHY - UMC 28HLP18 x1, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …
USB 2.0 femtoPHY - TSMC N5 12 x1, North/South (vertical) poly orientation
The USB 2.0 PHY IP provides designers with the industry's best combination of low area and low power with support for USB Type-C …