Vendor: Cadence Design Systems, Inc. Category: Protocol Bridge

Simulation VIP for AMBA DTI

Cadence provides a mature and comprehensive Verification IP (VIP)for theDistributed Translation Interface (DTI) specification, wh…

Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP)for theDistributed Translation Interface (DTI) specification, which is part of the Arm®AMBA®family of protocols. Incorporating the latestprotocol updates, the Cadence®Verification IP for DTI provides a complete bus functional model (BFM), integratedautomatic protocol checks, and coverage model.Designed for easy integration intestbenches at IP, system-on-chip (SoC), and system levels, the VIP for DTI helps youreduce time to test, accelerate verification closure, and ensure end-product quality. Cadence provides a solution for interconnect verification that verifies the correctness and completeness of data. The VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: AMBA® DTI r0p0 Edition 3. AMBA DTI Issue F Update.

Key features

  • Bypass Translation Mode Support
    • No translation happens via the TCU DTI VIP. Physical address will be the same as the Virtual address, and default attributes configured are used
  • Connect and Disconnect Message Group
    • The connection and disconnection of the DTI-TBU protocol channel
  • DTI-TBU Caching Module
    • The TBU implements a cache model in which translation response information is cached depending upon its intended function
  • Invalidation and Synchronization Message Group
    • Invalidation operations fo the TCU to indicate to the TBU that certain information must no longer be cached
  • Page Table Walk Support
    • TCU does a Page Table walk to determine the Physical address. User can load the page table entries through back door write
  • Random Mode Support
    • Translation request will be responded with random data in response
  • Register Access Message Group
    • The DTI TBU provides implementation defined registers, which can be accessed using these messages
  • Translation Request Message Group
    • The DTI-TBU translation requests messages to enable the TBU to find the translation for a given transaction or prefetch a translation

Block Diagram

Specifications

Identity

Part Number
Simulation VIP for AMBA DTI
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Protocol Bridge IP core

Cadence Expands Sovereign AI in Europe: From Chips to AI Factories

To bring computing scale and regional data control together, Cadence is expanding its sovereign AI data center in Munich, becoming the first electronic design automation (EDA)opens in a new tab vendor to deliver a comprehensive sovereign AI platform for semiconductor, system, and AI factory design in Europe.

The Memory Challenge of Physical AI

As physical AI workloads become more complex, architects must now consider how predictably the complete system performs when multiple real-world workloads are active simultaneously.

Frequently asked questions about Protocol Bridge IP cores

What is Simulation VIP for AMBA DTI?

Simulation VIP for AMBA DTI is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP