Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …
The 50G Ethernet Intel® FPGA IP core implements the 25G & 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Cons…
40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
This IP core implements the 25G and 50G Ethernet Specification, Draft 1.4 from the 25 Gigabit Ethernet Consortium.
1G/10Gb Ethernet PHY Intel® FPGA IP
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
Siemens EDA* AXI Verification IP Suite
The Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior an…
xSPI Multiple Bus Memory Controller
The industry ‘defacto standard’ memory controller for xSPI-like memories: HyperBus™ 1.0, 2.0 and 3.0 – OctaBus™ – Xccela® Bus – O…
Filtering with packet payload scanning Message filters are placed in the middle of a TCP / TLS session to scan application data, …
Full hardware TCP/UDP protocol stack realize both high performance and guaranteed delivery Our TCP/UDP offload engine supports si…
PCIe Gen 6 controller IP
GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.
MIPI A-PHY v1.0 is a physical layer communication protocol designed for automotive applications, including driver assistance, aut…
The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Comm…
The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performa…
Silvaco develops General Purpose I/O optimized for design flexibility, performance and ESD protection.
The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure …
USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification.
UCLe - Ensures reliable validation and efficient connectivity for chiplets
UCIe VIP is a solution for validating and ensuring compliance in multi-chip semiconductor systems.