The 1394 OVC is a fully documented, off-the-shelf component using the Open Verification Methodology for quickly enabling function…
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Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The 1394 OVC is a fully documented, off-the-shelf component using the Open Verification Methodology for quickly enabling function…
UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment.
USB OVA - USB 2.0 Function Controller OVA Checker IP
USB 2.0 Function Controller Checker OVA IP is fully documented, off the shelf component for the Developers of the USB 2.0 complia…
The USB 2.0 Vera RVM VIP is fully documented, off the shelf component for the Verification of the USB 2.0 compliant Function Cont…
The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect va…
The SafeSPI is a secure version of the SPI protocol that has been designed to provide enhanced security features, making it suita…
The SPI protocol specification supports high speed data transfer as per the peripheral specification, making it ideal for high - …
The I3c protocol, short for " Improved Inter - Integrated Circuit," is a communication protocol designed to improve upon the wide…
The I2C (Inter - Integrated Circuit) protocol is a widely used serial communication protocol for transferring data between electr…
DSP 10/100 100B-TX Ethernet PHY
SMS 10/100 ETHERNET PHY performs IEEE 802 10Base-T and 100Base-TX functionality as illustrated in Block diagram.
The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sub…
Intel® Stratix® 10 FPGA H-Tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compa…
Serial Lite III Streaming Intel® FPGA IP
The Serial Lite III Streaming Intel® FPGA Intellectual Property (IP) core offers simple connectivity that enables rapid point-to-…
Serial Lite II Intel® FPGA IP Core
The Serial Lite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at h…
The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duple…
Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II Intel offers two distinct Intel® FPGA IPs for …
Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP
Coordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs har…
Scalable Switch Intel® FPGA IP for PCI Express
The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream…
Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller I…
The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL…