Vendor: Altera Category: Ethernet

Triple-Speed Ethernet FPGA IP

The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sub…

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Overview

The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) Intellectual Property (IP). This IP function enables FPGAs to interface to an external Ethernet PHY device, which interfaces to the Ethernet network.

This IP is offered in MAC-only mode or in MAC+PHY mode. In the MAC only mode, the IP uses an external PHY chip to do signaling. The two supported interfaces to the external PHYs are: GMII (8-bit interface at 125 MHz SDR) and RGMII (4-bit interface at 125 MHz DDR).

In the MAC+PHY mode, the PHY is realized using on-chip transceivers or LVDS I/O with dynamic phase alignment (DPA) logic that can operate up to 1.25 Gbps. SGMII or 1000Base-X protocol is used in this case. The usage of LVDS I/Os enables very scalable multiport gigabit Ethernet (GbE) system designs while saving the serial transceivers for higher performance protocols.

Key features

  • Complete 10/100/1000 Mbps Ethernet IP with all the necessary IP modules
    • 10/100/1000 Mbps MAC, PCS, and PMA
  • Flexible IP options
    • MAC only, PCS only, MAC + PCS, MAC + PCS + PMA, PCS + PMA
    • Many options for various applications and sizes as small as 900 logic elements (small-MAC)
    • Standard-based statistics counters supporting simple network management protocol (SNMP) Management Information Base (MIB and MIB-II) and Remote Network Monitoring (RMON)
    • Parameterizable FIFO or FIFO-less MAC options
    • IEEE 1588 v2 high accuracy and high precision time stamping option in hardware IP
      • 1-step and 2-step time sync
      • Supports IEEE 1588 v2 PTP packet encapsulation in IPv4, IPv6, and Ethernet
      • Real time of day clock generator (ToD) IP in design example
  • Many external Ethernet interface options for various FPGA families
    • MII (10/100 Mbps), GMII, RGMII, and SGMII (10/100/1000 Mbps), 1000BASE-X, and TBI (1 Gbps)
    • Management data I/O (MDIO) for external PHY device management

Block Diagram

Triple-Speed Ethernet FPGA IP block diagram

Specifications

Identity

Part Number
Triple-Speed Ethernet FPGA IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about Ethernet IP core

Scalable architectures for high-bandwidth Ethernet line cards

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Frequently asked questions about Ethernet IP cores

What is Triple-Speed Ethernet FPGA IP?

Triple-Speed Ethernet FPGA IP is a Ethernet IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Ethernet?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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