Vendor: Altera Category: Video Transport

SDI II Intel® FPGA IP Core

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duple…

Contact Provider Request Datasheet

Overview

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

IP Core Feature

Description

Transceiver data interface

20 bit, 40 bit, and 80 bit

Supported SDI standards and video formats
  • Single Standard
  • Standard Definition or SD-SDI
  • High Definition or HD-SDI
  • 3 gigabits per second (Gbps) or 3G-SDI
  • Dual Link HD-SDI
  • Multiple Standards
  • Dual Standard up to HD-SDI
  • Triple Standard up to 3G-SDI
  • Multi Standard up to 12G-SDI

Note: Not all devices support all formats, see “Device Support” below

SMPTE support
  • SMPTE425M level A support (direct source image formatting)
  • SMPTE425M level B support (dual link mapping)

Other features
  • Payload identification packet insertion and extraction
  • Clock enable generator
  • Video rate detection
  • Cyclic redundancy check (CRC) encoding and decoding (except SD)
  • Dual link data stream synchronization (only HD)

Block Diagram

SDI II Intel® FPGA IP Core block diagram

What’s Included?

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel® FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control

Specifications

Identity

Part Number
SDI II Intel® FPGA IP Core
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about Video Transport IP core

Enabling High Performance SoCs Through Multi-Die Re-use

This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.

An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC)

This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.

Frequently asked questions about Video Transport IP cores

What is SDI II Intel® FPGA IP Core?

SDI II Intel® FPGA IP Core is a Video Transport IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP