Vendor: Altera Category: PCI Express

GTS PCIe Hard IP

Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller I…

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Overview

Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.

GTS PCIe Hard IP for PCI Express* Greatly Simplifies Design Integration for a Broad Range of Applications

  • Hardened IP blocks reduce logic resourcing allowing for higher user logic integration
  • Hardened IP blocks (complete protocol stack)
    • Transaction Layer / Data Link Layer / PHY Layer (MAC), and PHY (PCS and PMA)
    • SR-IOV (4 PFs, 256 VFs) enabling multiple applications on a single server - reducing Total Cost of Ownership (TCO)
  • Faster timing closure decreases time-to-market design cycles
  • Easy-to-use Design Tool Kit (DTK) for diagnostic and debug testing of PCIe design

Key features

  • Full protocol stack including the Transaction, Data Link, and Physical Layers implemented as Hard IP
    • Up to 4.0 x8 support: (Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes)
  • PCIe* 3.0/4.0 (x8/x4/x2/x1) configurations with 1.0/2.0 configurations support via link down-training support
  • Separate reference clock with independent spread spectrum clocking (SRIS)
    • Separate reference clock with no spread spectrum clocking (SRNS)
  • Independent PERST#
  • Single Virtual Channel (VC)
  • Capability Registers
  • 512-byte Maximum Payload Size (MPS)
  • 4096-byte (4 KB) Maximum Read Request Size (MRRS)
  • 32/64-bit BAR support (Prefetchable/Non-Prefetchable)
  • Expansion ROM BAR support
  • Number of tags for x8 controller: 32/64/128/256
  • MSI-X Table (maximum 4096 across)
  • Atomic operations (Fetch/Add/Swap/CAS)
  • TL Bypass mode allows for optional 3rd party PCIe switch IP integration
  • Precision Time Measurement (PTM)
  • SR-IOV support (4 PFs, 256 VFs)
    • Function Level Reset (FLR)
  • VirtIO support for software-based virtualization
  • SpyGlass CDC analysis tool
  • AXI4-Stream for application data path
    • AXI4-Stream Source/Sink
  • AXI-Lite for control and status register responder interface

Block Diagram

GTS PCIe Hard IP block diagram

Specifications

Identity

Part Number
GTS PCIe Hard IP
Vendor
Altera
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Altera
HQ: USA
Contact Altera

Learn more about PCI Express IP core

Frequently asked questions about PCIe IP cores

What is GTS PCIe Hard IP?

GTS PCIe Hard IP is a PCI Express IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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