The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
- CXL
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
Best-in-class eUSB2v2 Verification IP for your IP, SoC, and system-level design testing.
xSPI in production since 2019 for many production designs.The Cadence® Memory Model Verification IP (VIP) for xSPI provides verif…
Used by all top market leaders semiconductor companies.The Cadence® Verification IP (VIP) for USB4 provides a capable verificatio…
The Cadence® Verification IP (VIP) for USB is a VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata.
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
Best-in-class UART Verification IP for your IP, SoC and system-level design testing.
This Cadence® Verification IP (VIP) provides support for the TileLink specification.
In production since 2016 for many production designs.
This Cadence® Verification IP (VIP) provides support for the SPI protocol.
Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the SPDIF protocol pro…
Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for SMBus provides a bus functional model (BFM), in…
The Cadence® Verification IP (VIP) for SAS is part of Cadence’s broad storage interface verification IP (VIP) portfolio.
In production since 2018 for many production designs.The Cadence® Verification IP (VIP) for Quad SPI provides verification of Q-S…
Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a bus functional model (BFM), in…
In production since 2011.
The Cadence® PIPE PHY Verification IP (VIP) provides a mature, capable verification solution for the PHY layer of complex protoco…
Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…
In production since 2011 for dozens of designs.
Simulation VIP for MIPI UniPro
Best-in-class MIPI® UniPro Verification IP for your IP, SoC, and System-Level Design Testing In production since 2011 on dozens o…